Version Found: DDR4 v2.1 (Rev. 1)
Version Resolved: See (Xilinx Answer 69035)
When upgrading a locked IP to a new version of Vivado, the following error message might be seen:
ERROR: [Mig 66-119] Phy core regeneration & stitching failed. Please check vivado.log and debug_core_synth.log files in the directory: /proj/ipmig2/rakeshb/Upgrade_Flow_testing_2016.1_to_2016.4/ddr4_cmc_50tests_upgrade/ddr4_cmc_50tests_upgrade/SN6_virtexuDDR4_926MHz_72bit_ecc_ssit_BFM_XSDB_EN/vivado/impl/SN6_virtexuDDR4_ooc_en_example/SN6_virtexuDDR4_example/SN6_virtexuDDR4_ooc_en_ex/SN6_virtexuDDR4_ex/SN6_virtexuDDR4_ex.runs/impl_1/.Xil/Vivado-29140-xhd-lin64re91/29140 to debug the problem.
Phase 1 Generate And Synthesize MIG Cores | Checksum: 16911367c
This error can occur as a result of the address width for the targeted DDR4 part changing between releases. Only the following DDR4 RDIMM parts are impacted:
If this error message is seen and you are targeting one of the impacted DDR4 RDIMM parts, then please regenerate the DDR4 IP from scratch in the new version of Vivado to resolve the issue.
Revision History:
11/17/2016 - Initial Release
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 69035 | UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues | N/A | N/A |
| AR# 68236 | |
|---|---|
| 日期 | 01/12/2018 |
| 状态 | Active |
| Type | 已知问题 |
| 器件 | |
| Tools | |
| IP | |