AR# 68267

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2016.4 Vivado Timing/Speed Files - UltraScale - How to address setup and hold violations found when running new speed files

描述

(Xilinx Answer 68169) is a Design Advisory for Kintex UltraScale FPGAs and Virtex UltraScale FPGAs which details the new minimum production speed specification version (Speed File) required for all designs.

If you have run timing with the new speed files and have hold violations, the next step is to use the script attached to this Answer Record to resolve the hold errors.

解决方案

Several solutions are available:

  • Recommended solution: migrate your project to Vivado 2016.4 and run the normal Synthesis and Implementation flow to fix all setup and hold violations.
  • Second solution: continue using an older Vivado release for your project, running Synthesis and Implementation.
    Then load the routed DCP in Vivado 2016.4 to run timing signoff (report_timing_summary) and fix any setup and hold violation by following the steps presented below.
    Once timing is closed, use Vivado 2016.4 to generate the bitstream.
  • Third solution: continue using an older Vivado release with the corresponding speed files patch (limited to certain Vivado releases, available upon request).

If setup and hold failures are observed on a routed DCP in Vivado 2016.4, you can use the fixSetupHold.tcl script attached to this Answer Record to resolve the timing errors.

  1. Save the script
  2. Open the routed DCP in Vivado
  3. In the Vivado Tcl console, navigate to the location of the script and source the script:
    source -notrace fixSetupHold.tcl
  4. Next run the script in the Tcl console:
    fixSetupHold
  5. If failures still occur contact Xilinx Technical Support


The script runs commands depending on if Hold violations only are found, or both Setup and Hold violations.


You can run the steps manually instead of via the script. On the opened, routed DCP, after the timing analysis fails with Hold violations or Setup and Hold violations, run the following commands:

Hold Violations only

1) rerun "route_design"

2) Run timing analysis in Vivado 2016.4

3) If failures still occur contact Xilinx Technical Support

Both Setup and Hold or Setup only violations

1) Run "Light Effort".

Run the following command:

route_design -directive Explore

2) If violations still occur run "Medium Effort".

Run the following commands in order:

route_design -directive Explore
  phys_opt_design -directive Explore

3) If violations still occur run "High Effort".

Run the following commands in order:

place_design -post_place_opt
route_design -directive Explore
phys_opt_design -directive Explore

4) Run timing analysis in Vivado 2016.4.

5) If failures still occur contact Xilinx Technical Support.


Note: Refer to the attached fixSetupHold.tcl script for an example of using light, medium, to high effort fixing. 


Revision History:

12/12/2016 Initial Release

附件

文件名 文件大小 File Type
fixSetupHold.tcl 5 KB TCL

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AR# 68267
日期 12/20/2016
状态 Active
Type 综合文章
器件
Tools
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