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AR# 68439

Zynq UltraScale - PL MicroBlaze is not detected in the XSDB

描述

I have a MicroBlaze on my Zynq UltraScale PL, which is properly clocked and reset. However, when I try to debug this in SDK, it is missing from the JTAG chain.

How can this be resolved?

解决方案

This is a known issue on the ES1 silicon and this issue only presents itself if the MDM ID code SRL16s is set to a certain LOC. 

To work around this, change the LOC to another location.

You can put the following constraints in the top-level XDC file. The location used is known to not exhibit this issue:

For Vivado 2016.3 and 2016.4:

set_property LOC SLICE_X58Y73 [get_cells design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_ID_SRL16E.SRL16E_ID_1/Use_unisim.MB_SRL16E_I1]
set_property LOC SLICE_X58Y73 [get_cells design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_ID_SRL16E.SRL16E_ID_2/Use_unisim.MB_SRL16E_I1]

For Vivado 2016.2:

set_property LOC SLICE_X58Y73 [get_cells design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_ID_SRL16E.SRL16E_ID_1]
set_property LOC SLICE_X58Y73 [get_cells design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_ID_SRL16E.SRL16E_ID_2]

Note: You many need to adjust the path prefix "design_1_i/mdm_1" depending on your actual design.

AR# 68439
日期 12/21/2016
状态 Active
Type 综合文章
器件
  • Zynq UltraScale+ MPSoC
Tools
  • Vivado Design Suite - 2016.4
  • Vivado Design Suite - 2016.3
  • Vivado Design Suite - 2016.2
IP
  • Microblaze
的页面