Starting in Vivado 2016.4, the upper 2GB DDR initialization is added when ECC is enabled.
However FSBL hangs due to this function. How do I prevent the hang from occurring?
This occurs because of an issue in Windows where all the 64-bit addresses are truncated to 32-bit (PCIe, DDR) in xparameters.h, leading the FSBL to hang during the upper DDR ECC initialization.
Linux hosts are not affected.
The work-around is to manually modify the xparameters.h as follow:
Before:
After:
This issue is fixed in Vivado 2017.1 and later versions.
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 68211 | Zynq UltraScale+ MPSoC - FSBL does not initialize above first 2GB of PS DDR when using ECC, causing program exceptions | N/A | N/A |
| AR# 68582 | |
|---|---|
| 日期 | 05/04/2017 |
| 状态 | Active |
| Type | 综合文章 |
| 器件 | |
| Tools | |