AR# 68603


LogiCORE IP MIPI D-PHY v3.0 (Rev. 1) – Slave Mode (Shared logic in example design) D-PHY RX IP does not work when it is sharing resources with Master mode (Shared Logic in core) D-PHY Receiver IP.


In a MIPI D-PHY multi-instance system, one of the MIPI D-PHY Receiver IP cores is configured for Master mode (Shared logic in core) and one (or) more D-PHY RX IP core(s) are configured for Slave mode (Shared logic in example design).

Slave mode core input signals, namely clkoutphy_in, system_rst_in and pll_lock_in are driven by the Master mode core output signals clkoutphy_out, system_rst_out and pll_lock_out respectively.

The Slave mode IP core(s) will not work if it is configured as described above.

Note: the same issue and the solution described here are applicable for an MIPI CSI-2 Receiver Subsystem.


This is a known issue in the LogiCORE IP MIPI D-PHY v3.0 (Rev. 1) in Vivado 2016.4 and will be resolved in Vivado 2017.1.

To work around this issue in the 2016.4 version, you will need to disconnect the system_rst_out signal:




Answer Number 问答标题 问题版本 已解决问题的版本
54550 LogiCORE IP MIPI D-PHY - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions N/A N/A
AR# 68603
日期 04/24/2018
状态 Archive
Type 综合文章
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