AR# 68618

UltraScale\UltraScale+ - High Speed SelectIO Timing Budget for Native mode


The UltraScale datasheet includes performance numbers.

For example in (DS892) v1.14:


What guidance is there on how to reach these speeds?


The example below is intended to meet the LVDS performance of 1600 Mbps.

The following timing budget breaks down the transmitter timing budget for an interface based on the HSSIO wizard for a single bank.

These numbers apply to all devices and are based on characterization data.

Transmitter Timing Budget:

Timing Budget for LVDS Transmitter:


Timing Budget for Single ended (VREF) Transmitter:


Package skew should be deskewed through the PCB routing similar to the guidelines common for memory devices.

Any uncompensated package skew will need to be added to the "Pkg Skew."

For example, the package skew (as reported by Vivado, for example when using "Export I/O Ports") is 30 ps for a byte group and 150 ps for a bank.

The package skews will vary for the bank that is being deskewed.

Signal integrity issues includes the rise/fall times and PCB routing and any SI effects caused by cabling/connectors.

SI related issues can be simulated using IBIS models or SPICE models.

Please note that the PLL/CLK accounts for the dedicated clock connections that exist between the PLLE3 and BITSLICE_CONTROL (CLKOUTPHY).

The transmit budget must take into account the receiver errors (RX) such as the setup/hold timing window. 

For example, from the receiver timing budget, the IOB, PHY and Pkg Skew.

Receiver Timing Budget:

For the receiver side, the Transmit Error Subtotal which accounts for the variation of the transmitter device will similarly be used for the receive budget.

Any uncompensated package skew will need to be added to the "Pkg Skew." Please note this receiver budget is for the differential inputs.

Timing Budget for LVDS Receiver:


Timing Budget for VREF Receiver:


The following receiver assumptions are additionally being made:

  • BISC is being used to deskew to the die pads which is why package skews must be accounted for externally
  • Delays are only being used for the ALIGN_DELAY associated with BISC. DELAY_VALUE should be set to 0 for both receiver and transmitter
  • Dynamic Phase Alignment should be considered separate and should include an additional 40 ps to account for alignment issues
  • Strobes can either be center aligned (RX_CLK_PHASE_P/RX_CLK_PHASE_N = SHIFT_0) or edge aligned (RX_CLK_PHASE_P/RX_CLK_PHASE_N = SHIFT_90)
  • Transmitter can either use OUTPUT_PHASE_90 = TRUE or FALSE
  • Channel jitter should be simulated and accounted for in the timing budget
  • DATA_WIDTH = 4 or 8
  • The receiver timing budget must take into account the Transmit errors (TX) such as the setup/hold timing window. For example from the transmitter timing budget, this would be the PLL/CLK, IOB, and PHY.

Worked example:

We have two FPGAs interfacing to each other, we will call them FPGA A and FPGA B, and both are Virtex UltraScale.

FPGA A to FPGA B is interfacing with LVDS links, with PCB routing compensating for the package flight times.

How much skew can it tolerate when running at 1600Mbps?

FPGA A is the TX, therefore the transmitter device loss (required by the Receiver Budget) = 214.9 from the Transmitter Timing Budget.

CH = must be estimated for your board, for the calculations using a value of 50ps. Do not use this value in your calculations, it must be an accurate estimation of your channel.

IOB = 52.5

PHY = 116.6

Pkg Skew = 0

CH = 50

TX = 214.9

Total = 434

At 1600Mbps the bit period = 625ps

Therefore the Remaining Window = 625-434 = 191ps

The amount of Skew the interface can tolerate is 191ps.

Note: if you wish to include some extra margin this should also be accounted for.

AR# 68618
日期 11/26/2018
状态 Active
Type 综合文章
器件 More Less