AR# 68620

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2017.1 High Speed SelectIO Wizard - How to connect multiple instances to support a multi-bank interface

描述

The High Speed SelectIO Wizard v3.2 has added the option to Enable Ports to Connect to Multiple Interfaces.

This allows users to build multi-bank interfaces. How do I connect these ports to enable a multi bank interface?

 

Note: this Answer Record should not be viewed in isolation.

For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)

解决方案

In version 3.2 of the High Speed SelectIO Wizard, additional ports have been added when the "Enable Ports to Connect Multiple Interfaces" checkbox is checked.

If using Multiple Interfaces in a single bank, then the  "Include PLL in core" checkbox should be unchecked.


The exact ports that are added will depend on the configuration of the core.

Additional ports added for multi-interface designs:
            tri_tbyte<#>                            //input wire [3:0] tri_tbyte<#>
app_clk                                    // input wire app_clk
multi_intf_lock_in                   // input wire multi_intf_lock_in
intf_rdy                                   // output wire intf_rdy

If "Include PLL in core has been unchecked", the PLL will need to be set up by the user. 

For an example of how to configure the PLL for an application, "Open IP Example Design" will create an example design complete with the PLL instantiation.

Native Mode Bring-up For Interface Using Multiple Banks:

shared_pll0_clkout<#>_in      // input wire shared_pll0_clkout0_in
shared_pll0_clkoutphy_in       // input wire shared_pll0_clkoutphy_in
shared_pll0_locked_in<#>      // input wire shared_pll0_locked_in
 

Native Mode Bring up For Interface Using Multiple Banks

When an interface spans multiple banks, the clocking and reset state machines for each bank must be modified to ensure the state machines are brought up at the same time.

An application clock (app_clk) will be used for loading data into the TX_BITSLICE. As shown in Figure TX_BITSLICE Application Clock, the TX_BITSLICE uses the dedicated clocking from the PLL for the transmit clock. 

The dedicated PLL clock provides optimal performance for the TX_BITSLICE. In the case of RX_BITSLICE, the app_clk is given as fifo_rd_clk to read the data from FIFO.




Figure TX_BITSLICE Application Clock


The High Speed SelectIO Wizard might use CLKOUT0/CLKOUT1 for the application clock which can be used when a single bank is used. 

In the case of multiple bank interfaces (see Figure Multi-bank Clocking below) a single clock source is used to drive the app_clk for each of the High Speed SelectIO Wizards.

For multi-bank designs, because the application clock is driven by the MMCM, each core will need to connect the app_clk to the MMCM as shown in Figure Multi-Bank Clocking below. 

The app_clk is used for logic that must be in the application clock domain such as intf_rdy or for data for TX_BITSLICE.



Note: To minimize clocks skews from the MMCM, when an interface spans 3 banks, the MMCM should be placed in the middle bank of 3 contiguous banks. 

This should serve the same purpose as placing the USER_CLOCK_ROOTin the clocking region of the middle bank.

 

The High Speed SelectIO Wizard uses the riu_clk for the Reset State Machine. To ensure multi-bank interfaces are aligned, all of the interfaces must be reset at the same time. 

Additionally the locked outputs from each of the PLLs must must be synchronized to the riu_clk clock domain and logically ANDed together. 

Use of the pll0_locked outputs from each of the cores must be synchronized outside of the core. The combined lock signal can then be connected to multi_intf_locked_in for all of the interfaces. These changes will allow the state machines to be reset together.

Because the configuration of the RX_BITSLICEs and TX_BITSLICEs affects the length of the reset sequence, each bank can complete the reset sequence at different times as indicated by rst_seq_done. 


To determine when all of the banks are ready, the rst_seq_done from all of the interfaces should be logically ANDed to create an interface ready (intf_rdy) signal. For each of the cores, intf_rdy has already been synchronized to the app_clk domain. 

All of the intf_rdy signals should be ANDed together to determine when all of the banks are ready, for example, as multibank_intf_rdy.

The combined intf_rdy signal (multibank_intf_rdy) should be used to control tbyte_in[3:0] (BITSLICE_CONTROL) for designs using TX_BITSLICE. This can be accomplished by connecting the combined intf_rdy to additional tri_tbyte# ports for the core.

For designs targeting RX_BITSLICE, the fifo_rd_en should only be used after the entire interface is ready and multibank_intf_rdy has gone high. 

For example, when app_clk is used for the fifo_rd_clk connections:

always @ (posedge app_clk)
            fifo_rd_en = multibank_intf_rdy ? fifo_empty_<furthest location> :1b0;
 

Note: Use the inverted fifo_empty signal of the used bit slice which is furthest away from the bit slice receiving the clock, and thus generating the fifo_wrclk_out through a flip-flop to all fifo_rd_en inputs of used bit slices.

Furthest away means the bit slice at the end of the clock backbone.

For more information see (Xilinx Answer 66142)

 

As a general requirement for receive interfaces, ensure alignment across Source Synchronous interfaces by having the RX CLK stopped until the RX VTC_RDY is asserted for a single bank. See (Xilinx Answer 66244).

Extending this to a multi bank interface, you should wait until all of the Intf_Rdy signals assert before starting the RX CLK.

For more information, see (Xilinx Answer 66244).

Summary of multi-bank requirements:

Multi-bank clocking changes:

  • PLLs for each of the High Speed SelectIO Wizard cores should be driven from a single MMCM clock source to minimize skews between the PLLs.
    As a result, if 3 banks were to be used, then the MMCM should be placed in the middle I/O Bank.
    Minimizing the clock skews to the different PLLs is more critical than controlling the input clock routing for the MMCM.

Reset State Machine:

  • All PLLs and reset state machines should be reset at the same time
  • Locked outputs from all banks must be combined and synchronized to the RIU clock domain.
    Because the locked signal is an input into the reset state machine which is driven by the RIU clock domain, the combined multi-bank locked signal must also be in the RIU clock domain.
  • Application must wait for the rst_seq_done from all banks before enabling the application (intf_rdy).
    This signal should be synchronized to the application clock domain and control tbyte_in[3:0] for transmit applications or fifo_rd_en for receive applications.


Native Mode Bring up For Multiple Interfaces in a Shared Bank


When a bank contains two different interfaces, all used BITSLICE_CONTROLs within the bank share common control signals requiring the Native Mode Bring-up to start at the same time.

Unused BITSLICE_CONTROLs are bypassed by default. A single common reset for the entire bank must be used.  Each interface may complete the bring-up sequence at different times.

The High Speed SelectIO Wizard must also be modified to ensure the critical steps of the bring-up sequence are synchronized between the interfaces.




 

Figure Multiple Interfaces in Shared Bank shows a design that uses two different interfaces with independent riu_clk connections. 

When sharing a bank, the riu_clks should not vary by more than 4 times to ensure the cascaded DLYRDY for the used BITSLICE_CONTROLs. 

For example if riu_clk1 is 200 MHz, then riu_clk2 must be at least 50 MHz. As a synchronous state machine, the input data should use the same clock as the state machine.


For example the locked (PLL) signals for both interfaces must be ANDed together and resynchronized to the interface's riu_clk source. Interface 1 should use the riu_clk1 clock domain and interface 2 will use the riu_clk2. 

The intf_rdy should be used to control tbyte_in[3:0] for designs using TX_BITSLICE. When using the High Speed SelectIO Wizard, the tri_tbyte#[3:0] inputs should be connected to intf_rdy signal.

For designs targeting RX_BITSLICE, the fifo_rd_en should only be used after intf_rdy has gone high. 

For example, when app_clk is used for the fifo_rd_clk connections:

always @ (posedge app_clk)
            fifo_rd_en = multibank_intf_rdy ? fifo_empty_<furthest location> :1b0;


Note: Use the inverted fifo_empty signal of the used bit slice which is furthest away from the bit slice receiving the clock, and thus generating the fifo_wrclk_out through a flip-flop to all fifo_rd_en inputs of used bit slices. 

Furthest away means the bit slice at the end of the clock backbone.

For further information see (Xilinx Answer 66142).

AR# 68620
日期 04/19/2017
状态 Active
Type 综合文章
器件 More Less
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