AR# 68750

Zynq UltraScale+ MPSoC - Errata Work-around Solutions


Which PS errata has Xilinx provided a fix for in its Standalone BSP or Linux solution?


This Answer Record provides high-level guidance to which work-arounds have been provided in Xilinx Standalone Board Support Package (BSP) and Linux drivers.

TBD - work-around to be determined.

Xilinx AnswerErrata IssueStandalone BSPLinuxUser Notes
(Xilinx Answer 68878)PMU Counter Values Might Be Inaccurate When Monitoring Certain EventsTBD
(Xilinx Answer 68874)An Eviction Might Overtake A Cache Clean OperationNo work-aroundNo work-aroundNot needed. Most use cases perform a clean and invalidate.
(Xilinx Answer 68875)A Store-Exclusive Instruction Might Pass When It Should FailNo work-aroundNo work-aroundNot needed because of the rarity of this condition.
(Xilinx Answer 68876)Loads Of Mismatched Size Might Not Be Single-Copy AtomicNo work-aroundNo work-aroundNot needed because of the rarity of this condition.
(Xilinx Answer 68877)Reads Of PMEVCNTR <n> Are Not Masked By HDCR.HPMNTBD
(Xilinx Answer 68880)AArch64 Unconditional Branch Might Jump To Incorrect AddressNo work-aroundNo work-aroundNot needed.
(Xilinx Answer 68882)Direct Branch Instructions Executed Before A Trace Flush Might Be Output In An Atom Packet After Flush AcknowledgmentTBD
(Xilinx Answer 68946)APB Data Is Not Masked When PSLVERR Is SetTBD
(Xilinx Answer 66115)Incorrect Prefetch In V7S ModeN/A
Fix available in 2017.1 Linux IOMMUwork-around available.
(Xilinx Answer 66116)Updating A Translation Entry To Change Page Size Might Cause Data CorruptionN/AFix available in 2017.1 Linux IOMMUwork-around available.
(Xilinx Answer 65853)Instruction Sequences Containing AES Instructions Might Produce Incorrect ResultsN/AN/ANo work-around available.
(Xilinx Answer 65854)Load Might Read Incorrect DataN/AFix available in 2017.1 available.
(Xilinx Answer 65855)Memory Locations Might Be Accessed Speculatively Due To Instruction Fetches When HCR.VM Is SetNo work-aroundNo work-around
No work-around available.
(Xilinx Answer 65857)Non-Allocating Reads Might Prevent A Store Exclusive From Passingwork-around present in present in available in ATF.
(Xilinx Answer 65858)Write Of JMCR In EL0 Does Not Generate An UNDEFINED ExceptionN/AN/AN/A
Boot and Configuration
(Xilinx Answer 68615)Boot From NAND Might Fail If There Is Data Corruption In The First Parameter PageNo work-aroundN/ANo work-around available.
Controller for PCI Express
(Xilinx Answer 68534)Sending Modified Compliance Pattern Requires Additional PCIe Register ProgrammingTBD
(Xilinx Answer 68535)PCIe DMA Status Update Might Happen After Interrupt Is GeneratedTBD
(Xilinx Answer 68536)Under Heavy Read Traffic Conditions, The AXI-PCIe Bridge Arbitration Algorithm Might Incorrectly Select A Winning RequestorTBD
(Xilinx Answer 68537)PCIe Logs Incorrect Header In AER RegisterTBD
(Xilinx Answer 68539)PCIe Generates Two Fatal Errors For Poisoned CfgWr TLPs
(Xilinx Answer 68540)PCIe Logs Incorrect Header In AER RegisterTBD
(Xilinx Answer 68541)Controller For PCI Express Might Not Exit From Loopback ModeTBD
(Xilinx Answer 68542)PCIe DMA Completion Error Status Bit From Aborted DMA Transfers Might Persist Through DMA Channel ResetTBD
DDR Controller
(Xilinx Answer 71707)DDR Memory Controller Minimum Data Rate Is 1,000 Mb/s N/AN/ANo SW work-around available. Update Vivado DDR clocking and re-export.
(Xilinx Answer 68543)DDR Memory Controller Does Not Meet tSTAB Requirement For DDR3/DDR4 RDIMMsN/A
No work-around available.
(Xilinx Answer 65865)Accessing Unimplemented Registers In DDR Controller Causes Slave ErrorN/AN/AUnimplemented addresses should not be accessed by software.
Gigabit Ethernet Controller
(Xilinx Answer 68546)Incorrect Transmission Of Pause Frames In Response To Reception Of Pause Frames With Unicast Or Known Multicast AddressNo work-aroundNo work-aroundNo work-around available. Not needed for this issue.
Graphics Processing Unit (GPU)
(Xilinx Answer 69051)Pixel Processor Write Boundary High Address Value Is Constant

(Xilinx Answer 69052)DMA Controller Always Marks Transactions As Secure

(Xilinx Answer 65869)Dynamically Changing Controller Mode To Master From A Previous Slave Mode Might Cause Unnecessary Transfer On The I2C BusNo work-aroundNo work-aroundNot needed unless dynamically changing mode to master from slave.
(Xilinx Answer 65875)
Multi-lane Link Alignment Of PCIe Might Require Greater Than One SKP OrderedSet

(Xilinx Answer 68547)PS-GTR Ignores PCIe SKP Ordered Set With Odd Boundary Alignment

Real-Time Processing Unit (RPU)
(Xilinx Answer 68548)Self-Modify Code In Non-Cacheable Memory Might Not Work With A Slow Memory SystemNo work-aroundN/ANo Software work-around available.
(Xilinx Answer 65878)Processor Might Deadlock Or Lose Data When Configured With Cache-ECCNo work-aroundN/ANo Software work-around available.
(Xilinx Answer 65879)Watch-point On A Load Or Store Multiple Might Be MissedTBDN/A
SATA Controller
(Xilinx Answer 68971)Switching From Slumber Or Partial Sleep To The Active State Does Not Always Work ProperlyN/Awork-around available
Software work-around available in the AHCI stack.
(Xilinx Answer 65880)Incorrect Indication Of Overflow As CRC ErrorN/ANo work-aroundNo Software work-around available.
(Xilinx Answer 65881)Incorrect SRST Completion Indication To SATA Host SoftwareN/ANo work-aroundNo Software work-around available.
(Xilinx Answer 65882)SATA Device Sleep State Is Not Supported In The ControllerN/Awork-around availableBypass devsleep support in drive inquiry results
SD/SDIO/eMMC Controller
(Xilinx Answer 68549)In An Asynchronous Multiprocessing Environment, The SD/SDIO Tap Delays Might Get Asynchronously Updated, Resulting In Incorrect Configuration Of Tap Delay SettingsNo work-aroundNo work-aroundwork-around not needed
(Xilinx Answer 68550)Default Value Of SDIO Auto-Tuning Refresh Register Is IncorrectN/ANo work-aroundNot urgent, work-around may be provided in future Linux release.
(Xilinx Answer 68551)SD Auto-Tuning Requires Received Data Buffer To Be Emptied By SoftwareNo work-aroundNo work-aroundwork-around not needed
(Xilinx Answer 65883)Switching From 64-Bit DMA Mode To 32-Bit DMA Mode Might Cause Incomplete Data TransferN/AN/A
Xilinx drivers do not support switching between DMA modes.
SPI Controller
(Xilinx Answer 65885)SPI Controller Might Not Update RX_NEMPTY Flag, Showing Incorrect Status Of The Receive FIFOSW work-around availableNo work-aroundNo Linux work-around as of 2017.1, may be fixed in future releases.
System Test and Debug

(Xilinx Answer 68879)ETM Might Assert AFREADY Before All Data Has Been OutputN/AN/AN/A
(Xilinx Answer 68883)ETM Might Lose Counter Events While Entering wfx ModeN/AN/AN/A
(Xilinx Answer 68884)ETM Might Trace An Incorrect Exception AddressN/AN/AN/A
(Xilinx Answer 68885)APB Access To ETM Space While Core Is In Retention Will Never CompleteN/AN/AN/A
(Xilinx Answer 68886)ETM Does Not Report IDLE State When Disabled And Using OS LockN/AN/AN/A
(Xilinx Answer 65887)ATB Asynchronous Bridge Breaks Discovery In Integration ModeN/AN/AN/A
(Xilinx Answer 65889)TPIU Fails To Output Sync After The Pattern Generator Is Disabled In Normal ModeN/AN/AN/A
(Xilinx Answer 65890)Reset State Of ATB Flush Acknowledge Is IncorrectN/AN/AN/A
(Xilinx Answer 65892)Timestamp Replicator Might Stall SynchronizationN/AN/AN/A
USB 2.0/3.0 Host and Device, and USB 2.0 OTG Controller
(Xilinx Answer 67667)System Might Hang During Suspend/Resume StagesN/Awork-around planned for 2017.3 Linux
work-around planned.
(Xilinx Answer 68553)The tPortConfiguration Timer Resets During Recovery, Violating USB 3.0 SpecificationN/ANo work-aroundNo work-around needed.
(Xilinx Answer 68554)USB 2.0 Host Controller Does Not Assert Port Reset In Resume StateN/ANo work-aroundwork-around for Linux may be provided in future release.
(Xilinx Answer 68555)Incorrect Assertion Of Hot Reset Might Occur In USB 3.0 Host ModeN/AFix available in XHCI available.
(Xilinx Answer 68556)Request For U3 Transition Might Get Dropped When The USB 3.0 Host Controller Transitions From U1 To U2 StateN/ANo work-aroundwork-around for Linux may be provided in future release.
(Xilinx Answer 68557)USB Full-Speed Device Does Not Enter Hibernation State During DisconnectN/ANo work-aroundwork-around for Linux may be provided in future release.



Answer Number 问答标题 问题版本 已解决问题的版本
68874 Zynq UltraScale+ MPSoC、APU — 收回可能会赶超高速缓存清除操作 N/A N/A
68878 Zynq UltraScale+ MPSoC、 APU — 监控某些事件时,PMU 计数器值可能不准确。 N/A N/A
68875 Zynq UltraScale+ MPSoC、APU — 在它失效时,存储专用指令可能会通过。 N/A N/A
68876 Zynq UltraScale+ MPSoC、APU — 不匹配量的加载可能不是单拷贝原子 N/A N/A
68877 Zynq UltraScale+ MPSoC、APU — 读取 PMEVCNTR<n> 不会被 HDCR.HPMN 屏蔽 N/A N/A
68880 Zynq UltraScale+ MPSoC、APU — AArch64 无条件转移可能会跳转至错误的地址 N/A N/A
68882 Zynq UltraScale+ MPSoC, APU — 在追踪清理前执行的直接转移指令可能会在一个原子中输出 N/A N/A
66115 Zynq UltraScale+ MPSoC、 APU — V7S 模式中的错误预取 N/A N/A
66116 Zynq UltraScale+ MPSoC — 更新一个变换条目,以改变页面大小,可能会引起数据损坏 N/A N/A
65853 Zynq UltraScale+ MPSoC、APU — 包含 AES 指令的指令顺序可能会生成错误的结果 N/A N/A
65854 Zynq UltraScale+ MPSoC、APU — 加载可能会读取错误的数据 N/A N/A
65855 Zynq UltraScale+ MPSoC、APU — 设置 HCR.VM 时,存储器位置可能会因为指令获取被不确定地访问 N/A N/A
65858 Zynq UltraScale+ MPSoC、APU — 在 EL0 中写入 JMCR,不生成未定义异常 N/A N/A
65857 Zynq UltraScale+ MPSoC、APU — 非分配读取可能会阻止一个专用存储通过 N/A N/A
68886 Zynq UltraScale+ MPSoC、APU、系统调试 — 在禁用和使用操作系统锁时,ETM 不报告 IDLE 状态 N/A N/A
68946 Zynq UltraScale+ MPSoC、APU — 设置 PSLVERR 时,APB 数据没有屏蔽 N/A N/A
68543 Zynq UltraScale+ MPSoC — PS DDR 存储器控制器不符合 DDR3/DDR4 RDIMM 的 tSTAB 要求 N/A N/A
65865 Zynq UltraScale+ MPSoC — 访问 DDR 控制器中的未实施寄存器会引起从设备错误 N/A N/A
68548 Zynq UltraScale+ MPSoC、RPU — 不可缓存存储器中的自修正代码可能对缓慢存储器不起作用 N/A N/A
65878 Zynq UltraScale+ MPSoC、RPU — 采用高速缓存 ECC 配置时,处理器可能会锁死,也可能会丢失数据 N/A N/A
65879 Zynq UltraScale+ MPSoC,RPU — 通过 store multiple 指令设置监视点访问不会配置掩码 N/A N/A
68879 Zynq UltraScale+ MPSoC、系统调试 — ETM 可能会在所有数据输出前断言 AFREADY N/A N/A
68883 Zynq UltraScale+ MPSoC、系统调试 — ETM 在进入 wfx 模式时,可能会丢失计数器事件 N/A N/A
68884 Zynq UltraScale+ MPSoC、系统调试 — ETM 可能会追踪错误的异常地址 N/A N/A
68885 Zynq UltraScale+ MPSoC、系统调试 — 一个 APB 在内核处于保持模式时对 ETM 空间进行访问,将永远不会完成 N/A N/A
65887 Zynq UltraScale+ MPSoC、系统调试 — CoreSight ATB 异步桥接器中断集成模式下的发现 N/A N/A
65890 Zynq UltraScale+ MPSoC、系统调试 — ATB 清理承认的重置状态是错误的 N/A N/A
69052 Zynq UltraScale+ MPSoC、Mali GPU — DMA 控制器总是将事务处理标为安全 N/A N/A
69051 Zynq UltraScale+ MPSoC、Mali GPU — 像素处理器写入边界高地址值为常数 N/A N/A
69053 Zynq UltraScale+ MPSoC — 视频编解码器单元 (VCU) — 解码一个 8K CAVLC 视频比特流可能会挂起 N/A N/A
68546 Zynq UltraScale+ MPSoC、GEM — 使用单点传送或多点传送地址响应暂停帧接受时错误地传输了暂停帧 N/A N/A
69341 Zynq UltraScale+ MPSoC — 视频编解码器单元 (VCU) — 启用采样自适应偏移 (SAO) 滤波器时,解码一个每行像素为 8K 的 HEVC 视频比特流,导致解码图像损毁。 N/A N/A
69340 Zynq UltraScale+ MPSoC — 视频编解码器单元 (VCU) — 解码一个每行像素超过 4K 的 4 或 4.1 级 HEVC 视频比特流,导致解码图像损毁 N/A N/A
70769 Zynq UltraScale+ MPSoC 处理系统的设计咨询 — 初始 DRAM 温度超过 85 度时,LPDDR3/LPDDR4 温度降额不起作用 N/A N/A
71707 Zynq UltraScale+ MPSoC 处理系统设计咨询 — DDR 内存控制器最低数据速率为 1,000 Mb/s N/A N/A
AR# 68750
日期 12/14/2018
状态 Active
Type 综合文章