AR# 6886: V1.5 COREGEN, VIRTEX, BLOCK RAM Block RAM-generated EDIF still contains "<>" bus delimiters when "( )" or "[ ]" were specified as the desired delimiters.
AR# 6886
V1.5 COREGEN, VIRTEX, BLOCK RAM Block RAM-generated EDIF still contains "<>" bus delimiters when "( )" or "[ ]" were specified as the desired delimiters.
General Description: The CORE Generator Block RAM EDIF still has <> bus delimiters in it when ( ) (parentheses) or [ ] (square brackets) were specified.
解决方案
Even when you specify a different bus delimiter format, there will still be angle bracket ("< >") bus delimiters in the EDIF netlist associated with Xilinx primitives These angle-bracketed bus delimiters are associated with lower-level Xilinx components that are used to build the RAM.
The only bus delimiters that will change when you specify a different format are those associated with the interface ports of the RAM that must interface with the EDIF produced by the third-party synthesis tool.