Version Found: MIG 7 Series v4.2
Version Resolved: See (Xilinx Answer 54025)
When creating a MIG design with a XC7S6 or XC7S15 Spartan-7 FPGA there will be a critical warning message during synthesis:
This error message is generated due to an error in Vivado where the MIG XADC option is enabled by default even though these two Spartan-7 devices do not have XADC instantiations.
To avoid this error message, when configuring the MIG core with a XC7S6 or XC7S15 device, on the "FPGA Options" page make sure that the XADC Instantiation option is set to Disabled.
For these devices it is OK to have the XADC Instantiation disabled due to the low maximum data rates supported by these devices.
The expected behavior of the MIG Configuration GUI in future releases will be to not show the XADC Instantiation option for these devices and to have the IP set the option to Disabled.
09/13/2019 - Initial Release