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AR# 6899

EXEMPLAR: How to lock I/O pins in the GUI, VHDL code, or a Tcl script.

Description

Keywords: pin, loc, pinlock, HDL code, Spectrum, Leonardo, bus

Urgency: Standard

General Description:
How do I lock down I/O pins to a bus or a signal in a VHDL file using
Exemplar's LeonardoSpectrum?

Note: Currently, Exemplar cannot lock I/O pins to a bus in Verilog.

解决方案

1

Using the Leonardo Spectrum GUI:

1. After doing a 'READ' goto the 'Constraints' Power Tab.
2. Click on the appropriate Input or Output sub-tab.
3. Choose the appropriate Port in the Input/Output Ports window.
4. Fill in the appropriate Pin Location entry. (ie. P14)
5. Click on the 'Apply' button.

2

--VHDL example
------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library exemplar;
use exemplar.exemplar_1164.all;


entity d_register is
port (CLK, DATAA: in STD_LOGIC;
DATAB: in STD_LOGIC_VECTOR(3 downto 0);
QA: out STD_LOGIC;
QB: out STD_LOGIC_VECTOR(3 downto 0));

-- locking to a single pin
attribute PIN_NUMBER of DATA: SIGNAL IS "P22";

-- locking to an array of pins
attribute ARRAY_PIN_NUMBER of DATAB: SIGNAL is ("P3", "P4", "P5");

end d_register;

architecture BEHAV of d_register is

begin

My_D_Reg: process (CLK, DATA)
begin
if (CLK'event and CLK='1') then
QA <= DATAA;
QB <= DATAB;
end if;
end process; -- End My_D_Reg

end BEHAV;
-----------------------------

3

In a Tcl script:

After a 'READ' and before 'OPTIMIZE" use the following attribute:

set_attribute -port port_name -name PIN_NUMBER -value pin_number

for example:

set_attribute -port DATA -name PIN_NUMBER -value P22

4

//Verilog example
//Note: array_pin_number does not work in Verilog code

module test_entity(clk, in1, out1);
input clk ;
input in1 ; // exemplar attribute in1 pin_number P10
output out1;
reg out1;

always @(posedge clk)
begin
out1 <= in1;
end
endmodule
AR# 6899
创建日期 06/28/1999
Last Updated 04/24/2007
状态 Archive
Type 综合文章