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AR# 69006

Zynq UltraScale+ MPSoC: SD Booting Checklist

描述

This is a list of required items, necessary actions, and points to be considered, when debugging SD booting on Zynq UltraScale+ MPSoC.

解决方案

Before opening a Service Request, collect all of the information requested below.

1) Which SD Configuration is used?


Zynq UltraScale+ supports two different SD configurations (SD 2.0 and SD 3.0). 

The difference is critical because it requires different board component and different Vivado Configuration.

See (UG1085) chapter 11 and 26.

Please provide the details of the SD configuration used and the board schematics.


2) Is Zynq Production Silicon?

Use XSCT to read:

  • The IDCODE from 0xFFCA0040
  • The PS_VERSION from 0xFFCA0044

Please provide IDCODE and PS_VERSION


3) Is the JTAG chain operating properly?


Use XSCT to try to connect to the CPU.

Here is a list of relevant ARs:

(Xilinx Answer 67740)XSDB (or any other JTAG user) needs to hold the TMS signal high for 5 TCK cycles to enable PL TAP linking to the JTAG chain.
(Xilinx Answer 67818)2016.3 PMUFW Loading via JTAG / SD Boot Modes and Running An Example


Please provide JTAG chain description (how many devices on the chain, how many Zynq, Zynq in cascade or independent JTAG, any level shifter in the chain). Report any XSCT error.


4) In which phase of booting is Zynq failing? BootROM or FSBL?

 

In order to determine this, use an image with FSBL debug prints enabled. #define FSBL_DEBUG_DETAILED in xfsbl_debug.h

 

If some printing comes out on the UART during boot:

 

Please provide a log of the FSBL print out on the UART. FSBL is a user application and can be easily debugged using SDK. Try to do a brief investigation before filing a Service Request.

  • If nothing comes out on the UART during boot, first double check the UART baudrate.

 

Please provide the status of INIT_B, PS_ERROR_OUT, CSU_BR_ERROR and BOOT_MODE_POR registers after the boot failure.

  • An easy way to provide this register dump is to use the attached .tcl script (boot_registers_log_revX_Y.tcl)

 


5) Is it working using u-boot?

 

Use the u-boot.elf pre-built from the latest released image on the wiki: http://www.wiki.xilinx.com/Zynq+Releases

mmc info, fatls, fatload, etc ...

A debug option could be to limit the SD interface speed to "standard" (25MHz) and see if the error persists.

Please provide the log of the mmc commands to exercise the SD using pre-built u-boot image from the wiki. Specify the u-boot version used.


6) Is the Xilinx stand-alone example working (xilffs)?

 

Some Debugging is required to understand where the example is failing (through the SDK debugger or by adding debug prints).

A debug option could be to limit the SD interface speed to "standard" (25MHz) and see if the error persists.

 

Report the type of failure in the Xilinx stand-alone example.


7) Is the Linux kernel having an issue (for example: mmc0: error -110 whilst)?

Try to add this device tree node to the SDHC in question to run the interface at 50MHz.

  • no-1-8-v;

If you assume the card has timing issues you can slow down the clock in Linux to 25MHz using the following device tree node:

  • broken-mmc-highspeed

 

See http://www.wiki.xilinx.com/SD+controller for more details.

附件

文件名 文件大小 File Type
boot_registers_log_rev1_1.tcl 2 KB TCL
AR# 69006
日期 05/31/2018
状态 Active
Type 综合文章
器件
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