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AR# 69011

UltraScale+ GTY Transceiver: TX and RX Latency Values

描述

This answer record provides the TX and RX latency values for the GTY transceiver in the Kintex/Virtex UltraScale+ FPGA and Zynq UltraScale+ MPSoC device families.

解决方案

 

 

 

 

 

 

 

TX:

Internal Data Width 16 20 32 40 64 80 Comments
Min Max Min Max Min Max Min Max Min Max Min Max  
TX Fabric Interface Fabric width Fabric width Fabric width Fabric width Fabric width Fabric width Double the * values if TX_FABINT_USRCLK_FLOP = 1b1 (Default is 0).  Parenthesized numbers apply when Asynchronous Gearbox  (Gearbox FIFO) is used.
16 32 20 40 32 64 40 80 64 128 80 160
16* 48 20* 60 32*     96 40* 120 64*     192 80* 240
(33*) (99) (66*) (198)
    128, 160 128, 160         TX Fabric Interface latency for PCIe Gen4 with 64-bit bridge option.  Latency alternates between these two values during normal operation.
PCIe 128B/130B Encoder         96-126               0 if bypass
8B/10B Encoder     20 20     40 40         0 if bypass
Synchronous Gearbox (Legacy Gearbox) 32 - 64 32 - 64     64 - 128 64 - 128     128 - 254 128 - 254     64B66B 0 if bypass.  Parenthesized range is for CAUI mode.
(64 - 128) (64 - 128) (128 - 256) (128 - 256)
32 - 66 32-66     64 - 130 64 - 130     128 - 257 128 - 257     64B67B 0 if bypass.  Parenthesized range is for CAUI mode.
(64 - 132) (64 - 132) (128 - 260) (128 - 260)
Asynchronous Gearbox (Gearbox FIFO)         309-340 309-340     353-416 353-416     64B66B only 0 latency when unused. When used, TX Phase FIFO is bypassed with 0 latency.  If non-default TXGBOX_FIFO_INIT_RD_ADDR (IRA) is used, add (4IRA)*66 UI to latency.  CAUI numbers are expected to be close to these ranges.
TX Phase FIFO  40 -56         (56-72)  40 -56          (56-72)  50-70          (70-90)  50-70          (70-90)  80-112      (112-144)  80-112      (112-144)  100-140     (140-180)  100-140     (140-180) 160-224     (224-288) 160-224     (224-288) 200-280          (280-360) 200-280          (280-360) Using TX FIFO.  Parenthesized value applies if TXFIFO_ADDR_CFG = HIGH.(Default LOW)
16 16 20 20 32 (0 when using Gearbox FIFO) 32 (0 when using Gearbox FIFO) 40 40 64 (0 when using Gearbox FIFO) 64 (0 when using Gearbox FIFO) 80 80 Bypassing TX FIFO.
To TX PCS/PMA boundary 16 16 20 20 32 32 40 40 64 64 80 80  
To Serializer 32 32 40 40 64 64 80 80 128 128 160 160 Using TX FIFO or Gearbox FIFO:  2 TX XCLK cycles (extra reg stage for improved setup margin).
8 8 10 10 16 16 20 20 32 32 40 40 Bypassing TX FIFO and Gearbox FIFO:  1/2 cycle into Serializer.
PMA 19 19 19 19 29 29 29 29 29 29 29 29 Serializer.
Total -- absolute minimum for a given internal data width 75 89 141 169 253 309 Fabric Interface (NxN) + TX FIFO bypass + To TX PCS/PMA boundary + To Serializer + PMA.
Total -- XAUI (8B/10B mode) with TX FIFO     169 229     329 449         Fabric Interface (min NxN, max 2NxN) + 8B10B + TX FIFO (latency variation after reset) + To TX PCS/PMA boundary + To Serializer + PMA.
Total PCIe Gen3 (128B/130B)         237-267 237-267             Fabric Interface (32x32) + 128B/130B Encoder + TX FIFO bypass + To TX PCS/PMA boundary + To Serializer + PMA.


Note:

1) Using TXGBOX_FIFO_LATENCY DRP Register

For 32-bit user data width and 32-bit internal data width:

Latency for TX asynchronous gearbox = (value read from DRP attribute TXGBOX_FIFO_LATENCY) * 1/8 [UI] + 65.5 [UI]

For 64-bit user data width and 64-bit internal data width:

Latency for TX asynchronous gearbox = (value read from DRP attribute TXGBOX_FIFO_LATENCY) * 1/8 [UI] + 131 [UI]

2) Using the Latency table for high line rates

In addition to the TX and RX latencies in the tables above:

  1. When TX and RX FIFO are bypassed.
    User will have to add additional 1 UI latency for each 1 Gbps increment in line rate beyond 2 Gbps to the PMA latency. ( TX path:0.3 UI, RX path:0.7 UI, Total:1.0 UI )
  2. When RX FIFO is enabled and TX FIFO is bypassed.
    User will have to add additional 2 UI latency for each 1 Gbps increment in line rate beyond 2 Gbps to the PMA latency.

 

For Example:

 

From the table, for a particular use case, if the total latency (TX data path + RX data path) results in 609.5 UI and If the intended line rate of operation is 10 Gbps, the user has to add 8 UI (1 UI * 8) when TX and RX FIFO are bypassed. 

So, the final latency is 609.5 UI + 8 UI = 617.5 UI.



RX:

Internal Data Width 16 20 32 40 64 80 Comments  
Min Max Min Max Min Max Min Max Min Max Min Max  
PMA 36.5 36.5 42.5 42.5 52.5 52.5 62.5 62.5 84.5 84.5 100.5 100.5 Deserializer.
PMA to PCS 0 0 0 0 0 0 0 0 0 0 0 0  RX FIFO used
8 8 10 10 16 16 20 20 32 32 40 40 RX FIFO bypass:  1/2 cycle latency.
Internal Parallel Loopback:  PCS TX to RX 16 16 20 20 32 32 40 40 64 64 80 80 For internal parallel loopback only when Rx FIFO is used.  Latency from To TX PCS/PMA boundary of TX Table.
Comma Alignment 32 55 40 69 64 103 80 129 128 [131] 160 [163] Variability covers multiple modes.  Parenthesized min is for XAUI.  Bracketed max is for RXSLIDE PMA mode with PCS shifter
[33] (60)  [41]  [65] (120)  [81]
16 16 20 20 32 32 40 40 64 64 80 80 No Comma Alignment
8B/10B Decoder     20 20     40 40         0 if bypass.
PCIe Decoder and Block Alignment (128B/130B)         97-127               Decoder is synchronous, but its latency varies continuously within this range during normal operation.
PCIe RX Elastic Buffer     See Table on PCIe section       Varies with configuration.
Elastic buffer 24+ 8xML

(ML = CLK_COR_
MIN_LAT)
40 + 8xML

(ML = CLK_COR_
MIN_LAT)
30 + 10xML
50 + 10xML
48 + 8xML
80 + 8xML
60 + 10xML
100 + 10xML
96 + 8xML 160 + 8xML 120 + 10xML 200 + 10xML 0 if bypass


See important note concerning CLK_COR_MIN_LAT following the table.
For 2 byte: 4 ML 6 (phase only)
                    11 ML 13 (clock correction)
**Use ML = 6 for calculation
For 4 byte :  8 ML 12 (phase only)
                      23 ML 27 (clock correction)     
**Use ML = 12 for calculation
For 8 byte:  16 ML 24 (phase only)
**Use ML = 24 for calculation
Note concerning CLK_COR_MIN_LAT:  the value ranges shown for CLK_COR_MIN_LAT in the table are simplified guidelines for the purpose of showing sample latency ranges in the table

Phase Only is for FAST MODE
Asynchronous Gearbox (Gearbox FIFO)         252-348        (IRA =4) 252-348       (IRA =4)     372-500      (IRA = 3 ) 372-500       (IRA = 3)     64B66B only 0 latency when unused.  If non-default RXGBOX_FIFO_INIT_RD_ADDR (IRA) is used, add (defaultIRA)*66 UI to latency.4 is the default value for 4-Byte and 3 is the default value for 8-Byte.   
Synchronous Gearbox (Legacy Gearbox) 16 - 49   32 - 97                                            (32 - 98)   66 - 193                                          (64 - 194)   64B66B 0 if bypass.  Parenthesized range is for CAUI mode.
16 - 50   32 - 98                                          (32-100)   67 - 196                                        (64-196)   64B67B 0 if bypass.  Parenthesized range is for CAUI mode.
RX Fabric Interface Fabric Width Fabric Width Fabric Width Fabric Width Fabric Width Fabric Width  
16 32 20 40 32 64 40 80 64 128 80 160
16* 48 20* 60 32*     96 40* 120 64*  192 80* 240 Fabric interface latency.  Double the * values if RX_FABINT_USRCLK_INT = 1b1 (Default is 0).  Parenthesized numbers apply when Gearbox FIFO is used.
(33*) (99)    (66*) (198)
  0, 16       0,32-33       0     Extra latency when using gearboxes (0 or 1 RXUSRCLK cycle), due to possible need for extra pipelining to align frame within fabric word.
    96, 128 96, 128       RX Fabric Interface latency for PCIe Gen4 with 64-bit bridge option.  Latency alternates between these two values during normal operation.
Total -- absolute minimum 77 93 133 163 245 301 PMA (round up) + PMA to PCS (FIFO bypass) + Comma Alignment bypass + Fabric Interface (NxN)
Total -- XAUI (highest latency mode)     233 302     443 572         PMA (round up) + PMA to PCS (zero-cycle setup) + Comma Alignment (XAUI mode) + 8B/10B + Elastic Buffer (latency variation after reset) + Fabric Interface (min NxN, max 2NxN)
Total PCIe Gen3 (Common Clock mode)         408-501               PMA (round up) + PMA to PCS (using Elastic Buffer) + RXSLIDE PMA mode (with Comma Alignment) + PCIe Gen3 Align/Decode + PCIe Elastic Buffer (excluding PPM variation) + Fabric Interface (32x32).


Note:
1) Using RXGBOX_FIFO_LATENCY DRP Register

 

For 32-bit user data width and 32-bit internal data width:

Latency for RX asynchronous gearbox = (value read from DRP attribute RXGBOX_FIFO_LATENCY) * 1/8 [UI] + 32 [UI]

For 64-bit user data width and 64-bit internal data width:

Latency for RX asynchronous gearbox = (value read from DRP attribute RXGBOX_FIFO_LATENCY) * 1/8 [UI] + 63 [UI]


2) Using COMMA_ALIGN_LATENCY DRP Register


To determine actual latency using the COMMA_ALIGN_LATENCY register, use the following procedure:


Latency = 2*Internal Data Width + DRP value from COMMA_ALIGN_LATENCY register.

3) Using the Latency table for high line rates


In addition to the TX and RX latencies in the tables above:

1) When TX and RX FIFO are bypassed.

User will have to add additional 1 UI latency for each 1 Gbps increment in line rate beyond 2 Gbps to the PMA latency. ( TX path:0.3 UI, RX path:0.7 UI, Total:1.0 UI )

2) When RX FIFO is enabled and TX FIFO is bypassed.

User will have to add additional 2 UI latency for each 1 Gbps increment in line rate beyond 2 Gbps to the PMA latency.

 

For example:

From the table, for a particular use case, if the total latency (TX data path + RX data path) results in 609.5 UI and If the intended line rate of operation is 10 Gbps, you will need to add 8 UI (1 UI * 8) when TX and RX FIFO are bypassed. 

So, the final latency is 609.5 UI + 8 UI = 617.5 UI.

AR# 69011
日期 12/10/2018
状态 Active
Type 综合文章
器件
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