AR# 69021

JESD204 - 2017.1 — UltraScale / UltraScale+ IBUFDS_GTE 输出不稳定


When using the JESD204 core and PHY with clock configuration using the refclk as the core clock, clock output instability from the IBUFDS_GTE might be seen.


The IBUFDS_GTE which feeds the core_clk cannot be guaranteed to be stable until 250 us after the device configuration completes.

For this reason, the core and anything that is clocked by core_clk (for example, any AXI4-Stream logic) must be kept in reset for 250 us after device configuration completes.

This was fixed in the 2017.2 release for both the JESD204 IP and the JESD204_PHY IP with the addition of a signal called "gt_powergood".



Answer Number 问答标题 问题版本 已解决问题的版本
68804 LogiCORE IP JESD204C 核 - 发布说明与已知问题 N/A N/A
AR# 69021
日期 06/27/2020
状态 活跃
Type 一般类