This answer record contains the Release Notes and Known Issues for the DDR4 UltraScale and UltraScale+ Cores and includes the following:
This Release Notes and Known Issues Answer Record is for the programmable logic DDR4 IP core supported in UltraScale and UltraScale+ based devices.
DDR4 IP Page
https://www.xilinx.com/products/intellectual-property/ddr4.htm
Xilinx Forums:
Please seek technical support via the Memory Interfaces Board. The Xilinx Forums are a great resource for technical support.
The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.
General Information:
Supported devices can be found in the following locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.
Table 1 correlates the core version to the first Vivado design tools release version in which it was included.
Table 1: Version
| DDR4 Version | Vivado Tools Version |
| v2.2 (Rev. 8) | 2019.2 |
| v2.2 (Rev. 7) | 2019.1 |
| v2.2 (Rev. 6) | 2018.3 |
| v2.2 (Rev. 5) | 2018.2 |
| v2.2 (Rev. 4) | 2018.1 |
| v2.2 (Rev. 3) | 2017.4 |
| v2.2 (Rev. 2) | 2017.3 |
| v2.2 (Rev. 1) | 2017.2 |
| v2.2 | 2017.1 |
| v2.1 (Rev. 1) | 2016.4 |
| v2.1 | 2016.3 |
| v2.0 (Rev. 1) | 2016.2 |
| v2.0 | 2016.1 |
| v1.1 | 2015.4 |
| v1.0 | 2015.3 |
| v7.1 | 2015.2 |
| v7.0 | 2015.1 |
| v6.1 | 2014.4 |
| v6.0 | 2014.3 |
| v5.0 (Rev. 1) | 2014.2 |
| v5.0 | 2014.1 |
For a list of supported memory interfaces and operating frequencies for UltraScale family FPGAs go to the External Memory Interfaces section of the Memory Solutions Page.
For a complete list of supported DDR4 memory devices refer to the memory_device_support_ddr4.xlsx attachment found at the bottom of this Answer Record.
For the latest info on what is new for Vivado, including supported operating systems and IP release notes, see (UG973).
Known and Resolved Issues:
Table 2 provides the known and resolved issues for the UltraScale family DDR4 IP.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Table 2: Known and Resolved Issues
| Answer Record | Title | Version Found | Version Resolved | |
| (Xilinx Answer 73068) | Design Advisory for UltraScale/UltraScale+ DDR4/DDR3 IP - Memory IP Timing Exceptions which Manifest in Multiple Error Modes Introduced in Vivado 2018.3 and Later Versions | v2.2 (Rev. 6) |
v2.2 (Rev. 9) | |
| (Xilinx Answer 73052) | UltraScale/UltraScale+ DDR3/DDR4 IP - [Mig 66-119] Phy Core Regeneration & Stitching Failed | v1.0 | v2.2 (Rev. 9) | |
| (Xilinx Answer 72789) | UltraScale/UltraScale+ DDR3/DDR4 IP - Usage Guidelines for Multiple High Frequency Save/Restore Cycles | v2.1 | NF | |
| (Xilinx Answer 72582) | UltraScale Memory IP - Space Grade Kintex UltraScale XQRKU060 Device Byte Planner Errors or MIG 66-99 Error in Bank 46 or Bank 25 | v2.2 (Rev. 7) | Not Resolved
|
|
| (Xilinx Answer 71778) | UltraScale/UltraScale+ DDR4/DDR3 IP - Unable to Enter Self-Refresh when User Refresh is Enabled | v2.2 (Rev. 4) | v2.2 (Rev. 7)
|
|
| (Xilinx Answer 71696) | UltraScale/UltraScale+ DDR4 - Add support for changing Refresh Parameters through Tcl flow | v2.2 (Rev. 5) |
NAB | |
| (Xilinx Answer 71531) | UltraScale/UltraScale+ DDR4 DDR3 Post Save Restore ECC errors multi-rank only | v2.1 (Rev. 1) | v2.2 (Rev. 6) | |
| (Xilinx Answer 70874) | UltraScale/UltraScale+ DDR4 IP - AXI Arbitration Improvements | V2.2 | v2.2 (Rev. 4) | |
| (Xilinx Answer 69573) | UltraScale/UltraScale+ DDR4 IP - 2017.x multi-controller designs fail calibration at WRITE_DQS_TO_DQ (complex) - IBUF_LOW_PWR attribute (2016.4 upgrade) | V2.2 | v2.2 (Rev. 2) | |
| (Xilinx Answer 69779) | UltraScale/UltraScale+ DDR4 Address Parity incorrectly generated hen targeting 3DS RDIMMs and LRDIMMs | v2.2 (Rev. 2) | NF |
|
| (Xilinx Answer 69458) | UltraScale DDR4 - JEDEC Spec Updates for tCK(avg) in Speed Bin Tables effects CL and CWL Values for DDR4-2133 and Higher Speed Grade Devices | v2.2 (Rev. 1) | NF | |
| (Xilinx Answer 69071) | UltraScale/UltraScale+ DDR4/DDR3 IP - Simulations using Unisim Models in NCSIM or using the ncinitialize Switch Gives Unexpected Results | v2.1 (Rev. 1) | NF | |
| (Xilinx Answer 68997) | UltraScale DDR4 - Unable to set data width to 80 for a x16 Wide Interface Component in custom CSV | v2.2 | ||
| (Xilinx Answer 68943) | UltraScale DDR4 - MT40A1G16WBU-083E component with xcku115-flvb2104-2-e fails to generate output products | v2.2 (EA) | v2.2 (Rev. 1) | |
| (Xilinx Answer 67956) | UltraScale/UltraScale+ DDR4/DDR3 - Supported configurations for Self Refresh and Save/Restore |
v2.1 | v2.2 (Rev. 1) | |
| (Xilinx Answer 67979) | UltraScale DDR4 - Design generation error occurs due to incorrect maximum MMCM VCO value for -1H speed grade |
v2.1 | NAB | |
| (Xilinx Answer 66471) | UltraScale DDR4 - Incorrect Write Recovery (WR) value programmed to Mode Register 0 (MR0) |
v1.1 | NF |
|
| (Xilinx Answer 68236) | UltraScale DDR4 - upgrading locked IP might fail for select RDIMMs |
v2.1 (Rev. 1) | NF | |
| (Xilinx Answer 68143) | UltraScale+ MPSoC DDR4 - Tactical Patch - IP GUI hangs and crashes for specific settings |
v2.1 | v2.1 (Rev. 1) | |
| (Xilinx Answer 67230) | UltraScale DDR4 - tREFI interval is incorrectly set | v2.0 | v2.1 (Rev. 1) | |
| (Xilinx Answer 67891) | UltraScale DDR4/DDR3 - Ping-Pong PHY behavioral simulations fail with data errors when using BFM simulation mode |
v2.0 (Rev. 1) | v2.1 | |
| (Xilinx Answer 67631) | UltraScale DDR4 - some parts use the incorrect memory speed grade |
v2.0 (Rev. 1) | v2.1 | |
| (Xilinx Answer 67455) | UltraScale DDR3/DDR4 - Tactical Patch - ECC signals are missing from the User Interface when ECC is enabled without AXI |
v2.0 (Rev. 1) | v2.1 | |
| (Xilinx Answer 67255) | UltraScale/UltraScale+ DDR4 - [Place 30-487] error may occur for some configurations |
v2.0 | v2.1 | |
| (Xilinx Answer 67008) | UltraScale DDR4 - Enabling DBI Read causes Read Complex register values in XSDB BRAM to not be populated |
v2.0 | v2.1 | |
| (Xilinx Answer 66937) | UltraScale/UltraScale+ DDR4 and DDR3 IP - UNISIM simulations fail when using Self Refresh and Self Restore options | v2.0 | NAB |
|
| (Xilinx Answer 66938) | UltraScale+ DDR4 - Usage of six or more DDP (Dual Die Package/Twin Die) components is limited to 2133Mbps operation |
v2.0 | v2.1 | |
| (Xilinx Answer 67544) | UltraScale DDR4/DDR3 - Tactical Patch - Data errors seen at user interface when using Normal Ordering Error |
v2.0 | v2.1 | |
| (Xilinx Answer 67054) | UltraScale/UltraScale+ DDR4 - Extra CK/CK# clock pair generated for some RDIMMs and LRDIMMs |
v2.0 | v2.1 | |
| (Xilinx Answer 66927) | UltraScale DDR4/DDR3 - BFM simulations have errors when using Self Refresh and Self Restore options |
v2.0 | v2.0 (Rev. 1) | |
| (Xilinx Answer 66560) | UltraScale/UltraScale+ DDR3 and DDR4 IP - IP Generation Fails when Custom Part CSV File is Loaded for Twin Die Component | v1.1 | v2.0 | |
| (Xilinx Answer 66554) | UltraScale+ DDR4 - a 300MHz reference input clock cannot be chosen for 1333MHz (750ps) output clock frequency |
v2.0 | v2.0 (Rev. 1) |
|
| (Xilinx Answer 65083) | UltraScale+ MPSoC DDR4/DDR3 - No DIMM support for XCZU2EG and XCZU3EG devices with the SBVA484 package |
v1.0 | v2.0 (Rev. 1) | |
| (Xilinx Answer 64774) | UltraScale DDR4 - SETUP/HOLD violations in the mmcm_clkout0 domain |
v7.0 | v2.0 | |
| (Xilinx Answer 65950) | UltraScale DDR4/DDR3 - Synplify PRO Synplify Pro Black Box Testing designs can fail in calibration | v1.0 | v2.0 | |
| (Xilinx Answer 65372) | UltraScale DDR4/DDR3 IP - Vivado GUI Simulations fail with data errors when using VCS simulator |
v1.0 | v2.0 | |
| (Xilinx Answer 64784) | UltraScale DDR4 - false DRC MIG-32# errors detected for sys_clk_p/n | v7.0 | v2.0 | |
| (Xilinx Answer 64856) | Design Advisory for UltraScale DDR4/DDR3 - PCB pull-down required on the DDR3 RESET# pin and on the DDR4 RESET_N pin to maintain logic low during memory initialization | v5.0 | v7.1 | |
| (Xilinx Answer 65790) | UltraScale DDR4/DDR3 - Tactical Patch - when using a Custom Memory part some timing parameters are not updated correctly | v1.0 | v1.1 | |
| (Xilinx Answer 65652) | UltraScale DDR3/DDR4 - AXI enabled designs incorrectly have data mask tied to GND during Read-Modify-Write commands |
v1.0 | v1.1 | |
| (Xilinx Answer 65493) | UltraScale DDR4/DDR3 - IP generation fails for configurations requiring more than 3 contiguous banks when targeting FGPA devices with half banks in between full banks |
v1.0 | v1.1 | |
| (Xilinx Answer 63667) | UltraScale DDR4 - VIOLATION: cmdWR seen for tCK = 833ps and speed bin = 833 when using Micron Memory Model | v7.0 | v2.0 | |
| (Xilinx Answer 62086) | UltraScale DDR4/DDR3 - Performance Traffic Generator only works with "ROW COLUMN BANK" Address mapping | v5.0 (Rev. 1) | v2.0 | |
| (Xilinx Answer 65261) | UltraScale DDR4/DDR3 - Tactical Patch - Dynamic DCI does not work for some devices | v7.1 | v1.0 | |
| (Xilinx Answer 65054) | UltraScale DDR4 - CAS Latency setting of 17 results in calibration failures during DQS Gate Calibration | v7.1 | v1.0 | |
| (Xilinx Answer 64887) | UltraScale DDR4/DDR3 -Tactical Patch - Errors occur when implementing a 2015.1 MIG (v7.0) IP in Vivado 2015.2 |
v7.0 | v1.0 | |
| (Xilinx Answer 64773) | UltraScale DDR4/DDR3 - customization GUI shows incorrect Enable Chip Select Pin option when recustomizing IP | v7.0 |
v1.0 |
|
| (Xilinx Answer 64615) | UltraScale DDR4/DDR3 - AXI Interface efficiency improvements for 2015.2 | v7.0 | v7.1 | |
| (Xilinx Answer 64306) | UltraScale DDR4 - Tactical Patch - Required calibration patch to resolve potential hardware failures due to incorrect DLL Reset during SDRAM initialization sequence (all configurations) and internal nibble clocking (x4 only) |
v7.0 | v7.1 | |
| (Xilinx Answer 64010) | UltraScale DDR4/DDR3 - memory controller can hang when in "Strict" mode | v7.0 | v7.1 | |
| (Xilinx Answer 64063) | UltraScale DDR4/DDR3 - DIMM tool tip incorrectly lists the density for the base component part | v7.0 | v7.1 | |
| (Xilinx Answer 63786) | UltraScale DDR4 - SPEC_VIOLATION tWR/tRTP tWR seen for tCK = 833ps and speed bin = 833 when using Micron Memory Model |
v7.0 | v7.0 | |
| (Xilinx Answer 63666) | UltraScale DDR4 - tCK SPEC_VIOLATIONs for tCK = 833ps and speed bin = 833 when using Micron Memory Model |
v7.0 | v7.0 | |
| (Xilinx Answer 63596) | UltraScale DDR4/DDR3/RLDRAM3 - HOLD violations might be seen when using 2014.4.1 | v6.1 | v7.0 | |
| (Xilinx Answer 63261) | UltraScale DDR3/DDR4/QDRII+ - Multi-driver errors found during LINT check |
v6.1 | v7.0 | |
| (Xilinx Answer 63240) | UltraScale DDR4/DDR3 - PHY Only Documentation - (PG150) includes incorrect usage of "rdDataEn" in relation to "per_rd_done" (periodic read operation) and "rmw_rd_done" (RMW Operation) | v6.1 | v7.0 | |
| (Xilinx Answer 62930) | UltraScale DDR4/DDR3 -Tactical Patch - tCCD and tRTW violations can cause data errors in multi-rank and DDR4 x16 configurations |
v6.1 | v7.0 | |
| (Xilinx Answer 63022) | UltraScale DDR4/DDR3 - Designs targeting dual rank DIMMs with address mirroring fail in hardware |
v6.0 | v7.0 | |
| (Xilinx Answer 62776) | UltraScale DDR4/DDR3 - ECC fault injection does not work |
v6.1 | v7.0 | |
| (Xilinx Answer 60528) | UltraScale DDR4/DDR3 - Vivado may fail to generate output products with 64-bit data width |
v5.0 | v7.0 | |
| (Xilinx Answer 62321) | UltraScale DDR4/DDR3 - User Interface ports direction incorrect in instantiation template |
v5.0 | v6.1 | |
| (Xilinx Answer 61988) | UltraScale DDR4/DDR3 - Hold violations may be seen on a path clocked by riu_clk |
v6.0 | v6.1 | |
| (Xilinx Answer 62050) | UltraScale DDR4/DDR3 - Can reset_n be allocated to an I/O or does it have to be within a memory interface bank? |
v5.0 | v6.1 | |
| (Xilinx Answer 61909) | UltraScale DDR3/DDR4 - app_wdf_data format clarification |
v6.0 | v6.1 | |
| (Xilinx Answer 60181) | UltraScale DDR4/DDR3 - Timing violations may occur at higher data rates |
v5.0 | v6.1 | |
| (Xilinx Answer 62080) | UltraScale DDR4 - AXI Narrow Burst simulations cause model warnings to be generated |
v5.0 | v6.0 | |
| (Xilinx Answer 61901) | UltraScale DDR3/DDR4 - memory model violations observed during simulation |
v5.0 (Rev. 1) | NAB | |
| (Xilinx Answer 61725) | UltraScale/UltraScale+ DDR4 - Micron DDR4 part name shown in MIG GUI is obsolete |
v5.0 (Rev. 1) | v6.0 | |
| (Xilinx Answer 60322) | UltraScale DDR4 - MIG tool incorrectly allows Internal VREF to be disabled for DDR4 interfaces. | v5.0 | v1.1 | |
| (Xilinx Answer 59948) | UltraScale DDR4/DDR3 - Incorrect clock connection on dbg_hub which can have a negative timing impact. |
v5.0 | v5.0 (Rev. 1) | |
Revision History:
| 04/18/2017 | Created separate Answer record for DDR4 |
| 06/12/2017 | Updated for 2017.2; Added (Xilinx Answer 68028),(Xilinx Answer 69291) |
| 06/22/2017 | Added (Xilinx Answer 69324) |
| 07/13/2017 | Added (Xilinx Answer 69458) |
| 07/31/2017 | Updated debugging link to (Xilinx Answer 68937) |
| 09/18/2017 | Updated AR formatting and linked (Xilinx Answer 69573) |
| 11/29/2017 | Updated for 2017.4 |
| 03/13/2018 | Updated for 2018.1 |
| 04/04/2018 | Added AR70874 |
| 09/20/2018 | Updated for 2018.3 |
| 01/23/2019 | Added AR71531; Added AR71778 |
| 05/02/2019 | Updated for 2019.1 |
| 09/19/2019 | Added (Xilinx Answer 72789( and (Xilinx Answer 72582), Updated for 2019. |
| 11/04/2019 | Added AR7169; Added AR69071 |
| 11/19/2019 | Added AR73052 |
| 03/23/2020 | Added AR73068 |
| 文件名 | 文件大小 | File Type |
|---|---|---|
| memory_device_support_ddr4.xlsx | 18 KB | XLSX |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 58435 | UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues | N/A | N/A |