AR# 69036

UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues

描述

This answer record contains the Release Notes and Known Issues for the DDR3 UltraScale and UltraScale+ cores and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

 

This Release Notes and Known Issues Answer Record is for the programmable logic DDR3+ IP core supported in UltraScale and UltraScale+ based devices.

DDR3 IP Page
https://www.xilinx.com/products/intellectual-property/ddr3.html

Xilinx Forums:

Please seek technical support via the Memory Interfaces Board. The Xilinx Forums are a great resource for technical support. 

The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.

解决方案

General Information

Supported devices can be found in the following locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

 

Table 1: Version

DDR3 VersionVivado Tools Version
v1.4 (Rev. 9)2020.1
v1.4 (Rev. 8)2019.2
v1.4 (Rev. 7)2019.1
v1.4 (Rev. 6)2018.3
v1.4 (Rev. 5)2018.2
v1.4 (Rev. 4)2018.1
v1.4 (Rev. 3)2017.4
v1.4 (Rev. 2)2017.3
v1.4 (Rev. 1)2017.2
v1.42017.1
v1.3 (Rev. 1)2016.4
v1.32016.3
v1.2 (Rev. 1)2016.2
v1.22016.1
v1.12015.4
v1.02015.3
v7.12015.2
v7.02015.1
v6.12014.4
v6.02014.3
v5.0 (Rev. 1)2014.2
v5.02014.1

For a list of supported memory interfaces and operating frequencies for UltraScale family FPGAs go to the External Memory Interfaces section of the Memory Solutions page

 

For a complete list of supported DDR3 memory devices refer to the memory_device_support_ddr3.xlsx attachment found at the bottom of this Answer Record.

For the latest info on what is new for Vivado, including supported operating systems and IP release notes, see (UG973).

Known and Resolved Issues

Table 2 provides the known and resolved issues for the UltraScale family DDR3 IP.

 

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Table 2: Known and Resolved Issues

 

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 73715)UltraScale/UltraScale+ DDR3/DDR4 IP - Locked IPs using Self-Refresh with RDIMMs Must be Upgraded to Vivado 2020.1 or Later when Brought in to Vivado 2020.1 and Laterv1.4 (Rev. 9)NF
(Xilinx Answer 73714)UltraScale/UltraScale+ Memory IP - Locked IPs from Earlier Versions of Vivado when Brought in to 2020.1 or Later Will Encounter Errors During Implementation or in Hardwarev1.4 (Rev. 9)NF
(Xilinx Answer 73068)Design Advisory for UltraScale/UltraScale+ DDR4/DDR3 IP - Memory IP Timing Exceptions May Manifest as Post Calibration Data Errors or DQS Gate Tracking Errors in Hardwarev1.3 (Rev. 1)v1.4 (Rev. 9)
(Xilinx Answer 73052)UltraScale/UltraScale+ DDR3/DDR4 IP - [Mig 66-119] PHY Core Regeneration and Stitching Failedv1.0Not Resolved
(Xilinx Answer 72789)UltraScale/UltraScale+ DDR3/DDR4 IP - Usage Guidelines for Multiple High Frequency Save/Restore Cyclesv1.3NF
(Xilinx Answer 72582)UltraScale Memory IP - Space Grade Kintex UltraScale XQRKU060 Device Byte Planner Errors or MIG 66-99 Error in Bank 46 or Bank 25v2.2 (Rev. 7)v1.4 (Rev. 9)
(Xilinx Answer 71531)UltraScale/UltraScale+ DDR4 DDR3 Post Save Restore ECC errors multi-rank onlyv2.2(Rev 5)v1.4 (Rev. 6)
(Xilinx Answer 69071)UltraScale/UltraScale+ DDR4/DDR3 IP - Simulations using UNISIM Models in NCSIM or using the ncinitialize Switch Gives Unexpected Resultsv1.3 (Rev. 1)NF
(Xilinx Answer 67956)UltraScale/UltraScale+ DDR4/DDR3 - Supported configurations for Self Refresh and Save/Restorev1.3v1.4
(Xilinx Answer 66927)UltraScale DDR4/DDR3 - BFM simulations have errors when using Self Refresh and Self Restore optionsv1.3v1.3 (Rev. 1)
(Xilinx Answer 67544)UltraScale DDR4/DDR3 - Tactical Patch - Data errors seen at user interface when using Normal Ordering Errorv1.2v1.3
(Xilinx Answer 67891)UltraScale DDR4/DDR3 - Ping-Pong PHY behavioral simulations fail with data errors when using BFM simulation modev1.2 (Rev. 1)v1.3
(Xilinx Answer 67455)UltraScale DDR3/DDR4 - Tactical Patch -  ECC signals are missing from the User Interface when ECC is enabled without AXIv1.2 (Rev. 1)v1.3
(Xilinx Answer 66937)UltraScale/UltraScale+ DDR4 and DDR3 IP - UNISIM simulations fail when using Self Refresh and Self Restore optionsv1.2NAB
(Xilinx Answer 65083)UltraScale+ MPSoC DDR4/DDR3 - No DIMM support for XCZU2EG and XCZU3EG devices with the SBVA484 packagev1.0v1.2 (Rev. 1)
(Xilinx Answer 66794)UltraScale DDR3 - Write errors may be seen in dual rank or dual slot configurations in Vivado 2015.3 or 2015.4 due to Dynamic ODT settingsv1.0v1.2
(Xilinx Answer 66560)UltraScale/UltraScale+ DDR3 and DDR4 IP - IP Generation Fails when Custom Part CSV File is Loaded for Twin Die Componentv1.1v2.0
(Xilinx Answer 65950)UltraScale DDR4/DDR3 - Synplify PRO Synplify Pro Black Box Testing designs can fail in calibration v1.0v1.2
(Xilinx Answer 65421)UltraScale DDR3 - tIS memory model violations on ADDR and BA occur when simulating DDR3 example_tb testbenchv5.0v1.2
(Xilinx Answer 65493)UltraScale DDR4/DDR3 - IP generation fails for configurations requiring more than 3 contiguous banks when targeting FGPA devices with half banks in between full banksv1.0v1.1
(Xilinx Answer 65790)UltraScale DDR4/DDR3 - Tactical Patch - when using a Custom Memory part some timing parameters are not updated correctlyv1.0v1.1
(Xilinx Answer 65652)UltraScale DDR3/DDR4 - AXI enabled designs incorrectly have data mask tied to GND during Read-Modify-Write commandsv1.0v1.1
(Xilinx Answer 65372)UltraScale DDR4/DDR3 IP - Vivado GUI Simulations fail with data errors when using VCS simulatorv1.0v1.2
(Xilinx Answer 64856)Design Advisory for UltraScale DDR4/DDR3 - PCB pull-down required on the DDR3 RESET# pin and on the DDR4 RESET_N pin to maintain logic low during memory initializationv5.0v7.1
(Xilinx Answer 62086)UltraScale DDR4/DDR3 - Performance Traffic Generator only works with "ROW COLUMN BANK" Address mappingv5.0 (Rev. 1)v1.2
(Xilinx Answer 65261)UltraScale DDR4/DDR3 - Tactical Patch - Dynamic DCI does not work for some devicesv7.1v1.0
(Xilinx Answer 64775)UltraScale DDR3 - tZQinit violations seen during DDR3 simulationsv7.1v1.0
(Xilinx Answer 64773)UltraScale DDR4/DDR3 - customization GUI shows incorrect Enable Chip Select Pin option when recustomizing IPv7.0v1.0
(Xilinx Answer 63787)UltraScale DDR3 - ERRORs in simulation are seen when using the Micron memory model for sg125 speed grade with CAS Latency = 9 and CAS Write Latency = 7v7.0v1.0
(Xilinx Answer 63852)UltraScale DDR3 - Use of HR banks requires update of the output_impedance of all ports using reset_property commandv7.0NAB
(Xilinx Answer 64655)UltraScale DDR3 - Tactical Patch - IP generation incorrectly enables address mirroring for dual rank DDR3 RDIMMsv7.0v7.1
(Xilinx Answer 64010)UltraScale DDR4/DDR3 - memory controller can hang when in "Strict" modev7.0v7.1
(Xilinx Answer 64146)UltraScale DDR3 - simulation warnings for 16Gb and 8Gb DDR3 TwinDie partsv7.0v7.1
(Xilinx Answer 64063)UltraScale DDR4/DDR3 - DIMM tool tip incorrectly lists the density for the base component partv7.0v7.1
(Xilinx Answer 63789)UltraScale DDR3 - (HR banks only) When targeting the top data rates supported for -2/-3 speed grades, it is required to target a memory device one speed grade faster than the target data ratev7.0v7.1
(Xilinx Answer 63261)UltraScale/UltraScale+ DDR3/DDR4/QDRII+ - Multi-driver errors found during LINT checkv6.1v7.0
(Xilinx Answer 63596)UltraScale DDR4/DDR3/RLDRAM3 - HOLD violations might be seen when using 2014.4.1v6.1v7.0
(Xilinx Answer 63240)UltraScale DDR4/DDR3 - PHY Only Documentation - (PG150) includes incorrect usage of "rdDataEn" in relation to "per_rd_done" (periodic read operation) and "rmw_rd_done" (RMW Operation)v6.1v7.0
(Xilinx Answer 62930)UltraScale DDR4/DDR3 -Tactical Patch - tCCD and tRTW violations can cause data errors in multi-rank and DDR4 x16 configurations v6.1v7.0
(Xilinx Answer 62776)UltraScale DDR4/DDR3 - ECC fault injection does not workv6.1v7.0
(Xilinx Answer 60528)UltraScale DDR4/DDR3 - Vivado may fail to generate output products with 64-bit data widthv5.0v7.0
(Xilinx Answer 62321)UltraScale DDR4/DDR3 - User Interface ports direction incorrect in instantiation templatev5.0v6.1
(Xilinx Answer 62050)UltraScale DDR4/DDR3 - Can reset_n be allocated to an I/O or does it have to be within a memory interface bank?v5.0v6.1
(Xilinx Answer 61909)UltraScale DDR3/DDR4 - app_wdf_data format clarificationv6.0v6.1
(Xilinx Answer 61901)UltraScale DDR3/DDR4 - memory model violations observed during simulationv5.0 (Rev. 1)NAB
(Xilinx Answer 61129)UltraScale DDR3 - "ERROR: tCK(avg) minimum violation"v5.0 (Rev. 1)v6.0
(Xilinx Answer 61988)UltraScale DDR4/DDR3 - Hold violations may be seen on a path clocked by riu_clkv6.0v6.1
(Xilinx Answer 59948)UltraScale DDR4/DDR3 - Incorrect clock connection on dbg_hub which can have a negative timing impact.v5.0v 5.0 (Rev. 1)

Revision History:

04/18/2017Created Separate Answer Record for DDR3
06/12/2017Updated for 2017.2; Added (Xilinx Answer 68028), (Xilinx Answer 69291)
06/22/2017Added (Xilinx Answer 69324)
07/31/2017Updated debugging link to (Xilinx Answer 68937)
09/18/2017Updated formatting and updated for 2017.3
11/29/2017Updated for 2017.4
03/13/2018Updated for 2018.1
09/20/2018Updated for 2018.3
05/02/2019Updated for 2019.1
09/19/2019Added (Xilinx Answer 72789) and (Xilinx Answer 72582), Updated for 2019.2
11/04/2019Added AR#69071
11/19/2019Added AR73052
03/26/2020Added DAAR 73068
05/27/2020Added AR73714; Added AR73715; Updated for 2020.1

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
58435 MIG UltraScale - IP Release Notes and Known Issues for Vivado 2014.1 and newer tool versions N/A N/A

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
67956 UltraScale/UltraScale+ DDR4/DDR3 - Supported configurations for Self Refresh and Save/Restore N/A N/A
66927 UltraScale DDR4/DDR3 - BFM simulations have errors when using Self Refresh and Self Restore options N/A N/A
67544 UltraScale DDR4/DDR3 - Tactical Patch - Data errors seen at user interface when using Normal Ordering Error N/A N/A
67891 UltraScale DDR4/DDR3 - Ping-Pong PHY behavioral simulations fail with data errors when using BFM simulation mode N/A N/A
67455 UltraScale DDR3/DDR4 - Tactical Patch - ECC signals are missing from the User Interface when ECC is enabled without AXI N/A N/A
65083 UltraScale+ MPSoC DDR4/DDR3 - No DIMM support for XCZU2EG and XCZU3EG devices with the SBVA484 package N/A N/A
66794 UltraScale DDR3 - Write errors may be seen in dual rank or dual slot configurations in Vivado 2015.3 or 2015.4 due to Dynamic ODT settings N/A N/A
65950 UltraScale DDR4/DDR3 - Synplify PRO Synplify Pro Black Box Testing designs can fail in calibration N/A N/A
65421 UltraScale DDR3 - tIS memory model violations on ADDR and BA occur when simulating DDR3 example_tb testbench N/A N/A
65493 UltraScale DDR4/DDR3 - IP generation fails for configurations requiring more than 3 contiguous banks when targeting FGPA devices with half banks in between full banks N/A N/A
65790 UltraScale DDR4/DDR3 - Tactical Patch - when using a Custom Memory part some timing parameters are not updated correctly N/A N/A
65652 UltraScale DDR3/DDR4 - AXI enabled designs incorrectly have data mask tied to GND during Read-Modify-Write commands N/A N/A
65372 UltraScale DDR4/DDR3 IP - Vivado GUI Simulations fail with data errors when using VCS simulator N/A N/A
64856 UltraScale DDR4/DDR3 的设计咨询 — DDR3 RESET# 引脚和 DDR4 RESET_N 引脚上所需的 PCB 下拉可在存储器初始化期间保持逻辑低电平 N/A N/A
62086 MIG UltraScale DDR4/DDR3 — 性能流量生成器只对“ROW COLUMN BANK”地址映射起作用 N/A N/A
65261 UltraScale DDR4/DDR3 - Tactical Patch - Dynamic DCI does not work for some devices N/A N/A
64775 UltraScale DDR3 - tZQinit violations seen during DDR3 simulations N/A N/A
64773 MIG UltraScale DDR4/DDR3 - customization GUI shows incorrect Enable Chip Select Pin option when recustomizing IP N/A N/A
63787 UltraScale DDR3 - ERRORs in simulation are seen when using the Micron memory model for sg125 speed grade with CAS Latency = 9 and CAS Write Latency = 7 N/A N/A
63852 UltraScale DDR3 - Use of HR banks requires update of the output_impedance of all ports using reset_property command N/A N/A
64655 UltraScale DDR3 — 战术补丁 — IP 生成错误地为双排 DDR3 RDIMM 启用了地址镜像 N/A N/A
64010 UltraScale DDR4/DDR3 — 内存控制器处于“Strict”模式下时可能会挂起 N/A N/A
64146 UltraScale DDR3 - simulation warnings for 16Gb and 8Gb DDR3 TwinDie parts N/A N/A
64063 UltraScale DDR4/DDR3 - DIMM tool tip incorrectly lists the density for the base component part N/A N/A
63789 UltraScale DDR3 - (HR banks only) When targeting the top data rates supported for -2/-3 speed grades, it is required to target a memory device one speed grade faster than the target data rate N/A N/A
63261 UltraScale DDR3/DDR4/QDRII+ - Multi-driver errors found during LINT check N/A N/A
63596 UltraScale DDR4/DDR3/RLDRAM3 - HOLD violations might be seen when using 2014.4.1 N/A N/A
63240 MIG UltraScale DDR4/DDR3 - PHY Only Documentation - (PG150) includes incorrect usage of "rdDataEn" in relation to "per_rd_done" (periodic read operation) and "rmw_rd_done" (RMW Operation) N/A N/A
62930 UltraScale DDR4/DDR3 -Tactical Patch - tCCD and tRTW violations can cause data errors in multi-rank and DDR4 x16 configurations N/A N/A
62776 UltraScale DDR4/DDR3 - ECC fault injection does not work N/A N/A
60528 UltraScale DDR4/DDR3 — Vivado 可能无法生成支持 64 位数据位宽的输出产品 N/A N/A
62321 UltraScale DDR4/DDR3 - User Inteface ports direction incorrect in instantiation template N/A N/A
62050 UltraScale DDR4/DDR3 - Can reset_n be allocated to an I/O or does it have to be within a memory interface bank? N/A N/A
61909 UltraScale DDR3/DDR4 - app_wdf_data format clarification N/A N/A
61129 UltraScale DDR3 - "ERROR: tCK(avg) minimum violation" N/A N/A
61988 UltraScale DDR4/DDR3 - Hold violations may be seen on a path clocked by riu_clk N/A N/A
59948 UltraScale DDR4/DDR3 - Incorrect clock connection on dbg_hub which can have a negative timing impact. N/A N/A
61901 UltraScale DDR3/DDR4 - memory model violations observed during simulation N/A N/A
60181 UltraScale DDR4/DDR3 - Timing violations can occur at higher data rates N/A N/A
63022 UltraScale DDR4/DDR3 - Designs targeting dual rank DIMMs with address mirroring fail in hardware N/A N/A
64887 UltraScale DDR4/DDR3 -Tactical Patch - Errors occur when implementing a 2015.1 MIG (v7.0) IP in Vivado 2015.2 N/A N/A
64615 UltraScale DDR4/DDR3 - AXI Interface efficiency improvements for 2015.2 N/A N/A
66937 UltraScale/UltraScale+ DDR4 and DDR3 IP - UNISIM simulations fail when using Self Refresh and Self Restore options N/A N/A
66560 UltraScale/UltraScale+ DDR3 and DDR4 IP - IP Generation Fails when Custom Part CSV File is Loaded for Twin Die Component N/A N/A
71531 UltraScale/UltraScale+ DDR4 DDR3 Post Save Restore ECC 错误仅限多排 N/A N/A
71697 UltraScale+ RFSoC DDR4/DDR3/RLDRAM3 - The FSVE1156 package allows incorrect data widths N/A N/A
72789 UltraScale/UltraScale+ DDR3/DDR4 IP - Usage Guidelines for Multiple High Frequency Save/Restore Cycles N/A N/A
72582 UltraScale 内存 IP — 航天级 Kintex UltraScale XQRKU 060 器件字节规划器错误或 Bank 46 或 Bank 25 中的 MIG 66-99 错误 N/A N/A
69071 UltraScale/UltraScale+ DDR4/DDR3 IP - Simulations using UNISIM Models in NCSIM or Using the ncinitialize Switch Gives Unexpected Results N/A N/A
73052 UltraScale/UltraScale+ DDR3/DDR4 IP - [Mig 66-119] Phy Core Regeneration and Stitching Failed N/A N/A
73068 面向 UltraScale/UltraScale+ DDR4/DDR3 IP 的设计咨询 - 存储器 IP 时序异常可能导致校准后硬件中出现数据错误或 DQS 门控跟踪错误 N/A N/A
73714 UltraScale/UltraScale+ Memory IP - Locked IPs from Earlier Versions of Vivado when Brought in to 2020.1 or Later Will Encounter Errors During Implementation or in Hardware N/A N/A
73715 UltraScale/UltraScale+ DDR3/DDR4 IP - Locked IPs using Self-Refresh with RDIMMs Must be Upgraded to Vivado 2020.1 or Later when Brought in to Vivado 2020.1 and Later N/A N/A
AR# 69036
日期 08/25/2020
状态 Active
Type 版本说明
器件 More Less
Tools
IP