AR# 69036

UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues

描述

This answer record contains the Release Notes and Known Issues for the DDR3 UltraScale and UltraScale+ cores and includes the following:

  • 通用信息
  • 已知和已解决的问题
  • 修订历史

  

This Release Notes and Known Issues Answer Record is for the programmable logic DDR3+ IP core supported in UltraScale and UltraScale+ based devices.

DDR3 IP Page

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解决方案



  • DDR3 IP Page
  • 通过 Vivado
    • Open Vivado, go to the IP Catalog, right click on the DDR3 IP, and then select Compatible Families

如欲查看新特性列表和所有版本添加的器件支持,请参见 Vivado 工具中提供该核的 Change Log 文件。

表 1 将内核版本关联至首个包含该表的 Vivado 设计工具发布版本。

  

表 1: 版本

Vivado 工具版本
2020.1
2019.2
2019.1
2018.3
2018.2
2018.1
2017.4
2017.3
2017.2
2017.1
2016.4
2016.3
2016.2
2016.1
2015.4
v1.02015.3
2015.2
v7.02015.1
v6.12014.4
v6.02014.3
2014.2
2014.1

  

For a complete list of supported DDR3 memory devices refer to the memory_device_support_ddr3.xlsx attachment found at the bottom of this Answer Record.

如欲了解有关 Vivado 最新特性的最新信息(包括支持的操作系统和 IP 版本说明),请参见 (UG973)

已知和已解决的问题

Table 2 provides the known and resolved issues for the UltraScale family DDR3 IP.

  

注: "找到的版本" 列出了首次发现问题的版本。该问题可能也出现于较早版本,但未对较早版本进行特定测试。

表 2:已知问题和已解决问题

  

答复记录标题发现问题的版本已解决问题的版本
UltraScale/UltraScale+ DDR3/DDR4 IP - Locked IPs using Self-Refresh with RDIMMs Must be Upgraded to Vivado 2020.1 or Later when Brought in to Vivado 2020.1 and Laterv1.4 (Rev. 9)NF
UltraScale/UltraScale+ Memory IP - Locked IPs from Earlier Versions of Vivado when Brought in to 2020.1 or Later Will Encounter Errors During Implementation or in Hardwarev1.4 (Rev. 9)NF
Design Advisory for UltraScale/UltraScale+ DDR4/DDR3 IP - Memory IP Timing Exceptions May Manifest as Post Calibration Data Errors or DQS Gate Tracking Errors in Hardwarev1.4 (Rev. 6)v1.4 (Rev. 9)
UltraScale/UltraScale+ DDR3/DDR4 IP - [Mig 66-119] Phy Core Regeneration & Stitching Failedv1.0未解决
UltraScale/UltraScale+ DDR3/DDR4 IP - Usage Guidelines for Multiple High Frequency Save/Restore Cyclesv1.3NF
UltraScale 内存 IP — 航天级 Kintex UltraScale XQRKU 060 器件字节规划器错误或 Bank 46 或 Bank 25 中的 MIG 66-99 错误v2.2 (Rev. 7)v1.4 (Rev. 9)
UltraScale/UltraScale+ DDR4 DDR3 Post Save Restore ECC 错误仅限多排v2.2(Rev 5)v1.4 (Rev. 6)
UltraScale/UltraScale+ DDR4/DDR3 IP - Simulations using UNISIM Models in NCSIM or using the ncinitialize Switch Gives Unexpected Resultsv1.3 (Rev. 1)NF
UltraScale/UltraScale+ DDR4/DDR3 - Supported configurations for Self Refresh and Save/Restorev1.3v1.4
UltraScale DDR4/DDR3 - BFM simulations have errors when using Self Refresh and Self Restore optionsv1.3v1.3 (Rev. 1)
UltraScale DDR4/DDR3 - Tactical Patch - Data errors seen at user interface when using Normal Ordering Errorv1.2v1.3
UltraScale DDR4/DDR3 - Ping-Pong PHY behavioral simulations fail with data errors when using BFM simulation modev1.2 (Rev. 1)v1.3
UltraScale DDR3/DDR4 - Tactical Patch -  ECC signals are missing from the User Interface when ECC is enabled without AXIv1.2 (Rev. 1)v1.3
UltraScale/UltraScale+ DDR4 and DDR3 IP - UNISIM simulations fail when using Self Refresh and Self Restore optionsv1.2NAB
UltraScale+ MPSoC DDR4/DDR3 - No DIMM support for XCZU2EG and XCZU3EG devices with the SBVA484 packagev1.0v1.2 (Rev. 1)
UltraScale DDR3 - Write errors may be seen in dual rank or dual slot configurations in Vivado 2015.3 or 2015.4 due to Dynamic ODT settingsv1.0v1.2
UltraScale/UltraScale+ DDR3 and DDR4 IP - IP Generation Fails when Custom Part CSV File is Loaded for Twin Die Componentv1.1v2.0
UltraScale DDR4/DDR3 - Synplify PRO Synplify Pro Black Box Testing designs can fail in calibration v1.0v1.2
UltraScale DDR3 - tIS memory model violations on ADDR and BA occur when simulating DDR3 example_tb testbenchv5.0v1.2
UltraScale DDR4/DDR3 - IP generation fails for configurations requiring more than 3 contiguous banks when targeting FGPA devices with half banks in between full banksv1.0v1.1
UltraScale DDR4/DDR3 - Tactical Patch - when using a Custom Memory part some timing parameters are not updated correctlyv1.0v1.1
UltraScale DDR3/DDR4 - AXI enabled designs incorrectly have data mask tied to GND during Read-Modify-Write commandsv1.0v1.1
UltraScale DDR4/DDR3 IP - Vivado GUI Simulations fail with data errors when using VCS simulatorv1.0v1.2
UltraScale DDR4/DDR3 的设计咨询 — DDR3 RESET# 引脚和 DDR4 RESET_N 引脚上所需的 PCB 下拉可在存储器初始化期间保持逻辑低电平v5.0v7.1
UltraScale DDR4/DDR3 - Performance Traffic Generator only works with "ROW COLUMN BANK" Address mappingv5.0 (Rev. 1)v1.2
UltraScale DDR4/DDR3 - Tactical Patch - Dynamic DCI does not work for some devicesv7.1v1.0
UltraScale DDR3 - tZQinit violations seen during DDR3 simulationsv7.1v1.0
UltraScale DDR4/DDR3 - customization GUI shows incorrect Enable Chip Select Pin option when recustomizing IPv7.0v1.0
UltraScale DDR3 - ERRORs in simulation are seen when using the Micron memory model for sg125 speed grade with CAS Latency = 9 and CAS Write Latency = 7v7.0v1.0
UltraScale DDR3 - Use of HR banks requires update of the output_impedance of all ports using reset_property commandv7.0NAB
UltraScale DDR3 — 战术补丁 — IP 生成错误地为双排 DDR3 RDIMM 启用了地址镜像v7.0v7.1
UltraScale DDR4/DDR3 — 内存控制器处于“Strict”模式下时可能会挂起v7.0v7.1
UltraScale DDR3 - simulation warnings for 16Gb and 8Gb DDR3 TwinDie partsv7.0v7.1
UltraScale DDR4/DDR3 - DIMM tool tip incorrectly lists the density for the base component partv7.0v7.1
UltraScale DDR3 - (HR banks only) When targeting the top data rates supported for -2/-3 speed grades, it is required to target a memory device one speed grade faster than the target data ratev7.0v7.1
UltraScale/UltraScale+ DDR3/DDR4/QDRII+ - Multi-driver errors found during LINT checkv6.1v7.0
UltraScale DDR4/DDR3/RLDRAM3 — 使用 2014.4.1 时可能会出现 HOLD 违规v6.1v7.0
UltraScale DDR4/DDR3 - PHY Only Documentation - (PG150) includes incorrect usage of "rdDataEn" in relation to "per_rd_done" (periodic read operation) and "rmw_rd_done" (RMW Operation)v6.1v7.0
UltraScale DDR4/DDR3 -Tactical Patch - tCCD and tRTW violations can cause data errors in multi-rank and DDR4 x16 configurations v6.1v7.0
UltraScale DDR4/DDR3 - ECC fault injection does not workv6.1v7.0
UltraScale DDR4/DDR3 - Vivado may fail to generate output products with 64-bit data widthv5.0v7.0
UltraScale DDR4/DDR3 - User Interface ports direction incorrect in instantiation templatev5.0v6.1
UltraScale DDR4/DDR3 - Can reset_n be allocated to an I/O or does it have to be within a memory interface bank?v5.0v6.1
UltraScale DDR3/DDR4 - app_wdf_data format clarificationv6.0v6.1
UltraScale DDR3/DDR4 - memory model violations observed during simulationv5.0 (Rev. 1)NAB
UltraScale DDR3 - "ERROR: tCK(avg) minimum violation"v5.0 (Rev. 1)v6.0
UltraScale DDR4/DDR3 - Hold violations may be seen on a path clocked by riu_clkv6.0v6.1
UltraScale DDR4/DDR3 - Incorrect clock connection on dbg_hub which can have a negative timing impact.v5.0v 5.0 (Rev. 1)

修订历史:

Created Separate Answer Record for DDR3
更新了格式化并针对 2017.3 进行了更新
2017.4 更新
2018.1 更新
2018.3 更新
05/02/20192019.1 更新
Added AR#69071
Added AR73052
Added DAAR 73068
Added AR73714; Added AR73715; Updated for 2020.1

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
58435 MIG UltraScale - IP Release Notes and Known Issues for Vivado 2014.1 and newer tool versions N/A N/A

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
67956 UltraScale/UltraScale+ DDR4/DDR3 - Supported configurations for Self Refresh and Save/Restore N/A N/A
66927 UltraScale DDR4/DDR3 - BFM simulations have errors when using Self Refresh and Self Restore options N/A N/A
67544 UltraScale DDR4/DDR3 - Tactical Patch - Data errors seen at user interface when using Normal Ordering Error N/A N/A
67891 UltraScale DDR4/DDR3 - Ping-Pong PHY behavioral simulations fail with data errors when using BFM simulation mode N/A N/A
67455 UltraScale DDR3/DDR4 - Tactical Patch - ECC signals are missing from the User Interface when ECC is enabled without AXI N/A N/A
65083 UltraScale+ MPSoC DDR4/DDR3 - No DIMM support for XCZU2EG and XCZU3EG devices with the SBVA484 package N/A N/A
66794 UltraScale DDR3 - Write errors may be seen in dual rank or dual slot configurations in Vivado 2015.3 or 2015.4 due to Dynamic ODT settings N/A N/A
65950 UltraScale DDR4/DDR3 - Synplify PRO Synplify Pro Black Box Testing designs can fail in calibration N/A N/A
65421 UltraScale DDR3 - tIS memory model violations on ADDR and BA occur when simulating DDR3 example_tb testbench N/A N/A
65493 UltraScale DDR4/DDR3 - IP generation fails for configurations requiring more than 3 contiguous banks when targeting FGPA devices with half banks in between full banks N/A N/A
65790 UltraScale DDR4/DDR3 - Tactical Patch - when using a Custom Memory part some timing parameters are not updated correctly N/A N/A
65652 UltraScale DDR3/DDR4 - AXI enabled designs incorrectly have data mask tied to GND during Read-Modify-Write commands N/A N/A
65372 UltraScale DDR4/DDR3 IP - Vivado GUI Simulations fail with data errors when using VCS simulator N/A N/A
64856 UltraScale DDR4/DDR3 的设计咨询 — DDR3 RESET# 引脚和 DDR4 RESET_N 引脚上所需的 PCB 下拉可在存储器初始化期间保持逻辑低电平 N/A N/A
62086 MIG UltraScale DDR4/DDR3 — 性能流量生成器只对“ROW COLUMN BANK”地址映射起作用 N/A N/A
65261 UltraScale DDR4/DDR3 - Tactical Patch - Dynamic DCI does not work for some devices N/A N/A
64775 UltraScale DDR3 - tZQinit violations seen during DDR3 simulations N/A N/A
64773 MIG UltraScale DDR4/DDR3 - customization GUI shows incorrect Enable Chip Select Pin option when recustomizing IP N/A N/A
63787 UltraScale DDR3 - ERRORs in simulation are seen when using the Micron memory model for sg125 speed grade with CAS Latency = 9 and CAS Write Latency = 7 N/A N/A
63852 UltraScale DDR3 - Use of HR banks requires update of the output_impedance of all ports using reset_property command N/A N/A
64655 UltraScale DDR3 — 战术补丁 — IP 生成错误地为双排 DDR3 RDIMM 启用了地址镜像 N/A N/A
64010 UltraScale DDR4/DDR3 — 内存控制器处于“Strict”模式下时可能会挂起 N/A N/A
64146 UltraScale DDR3 - simulation warnings for 16Gb and 8Gb DDR3 TwinDie parts N/A N/A
64063 UltraScale DDR4/DDR3 - DIMM tool tip incorrectly lists the density for the base component part N/A N/A
63789 UltraScale DDR3 - (HR banks only) When targeting the top data rates supported for -2/-3 speed grades, it is required to target a memory device one speed grade faster than the target data rate N/A N/A
63261 UltraScale DDR3/DDR4/QDRII+ - Multi-driver errors found during LINT check N/A N/A
63596 UltraScale DDR4/DDR3/RLDRAM3 - HOLD violations might be seen when using 2014.4.1 N/A N/A
63240 MIG UltraScale DDR4/DDR3 - PHY Only Documentation - (PG150) includes incorrect usage of "rdDataEn" in relation to "per_rd_done" (periodic read operation) and "rmw_rd_done" (RMW Operation) N/A N/A
62930 UltraScale DDR4/DDR3 -Tactical Patch - tCCD and tRTW violations can cause data errors in multi-rank and DDR4 x16 configurations N/A N/A
62776 UltraScale DDR4/DDR3 - ECC fault injection does not work N/A N/A
60528 UltraScale DDR4/DDR3 — Vivado 可能无法生成支持 64 位数据位宽的输出产品 N/A N/A
62321 UltraScale DDR4/DDR3 - User Inteface ports direction incorrect in instantiation template N/A N/A
62050 UltraScale DDR4/DDR3 - Can reset_n be allocated to an I/O or does it have to be within a memory interface bank? N/A N/A
61909 UltraScale DDR3/DDR4 - app_wdf_data format clarification N/A N/A
61129 UltraScale DDR3 - "ERROR: tCK(avg) minimum violation" N/A N/A
61988 UltraScale DDR4/DDR3 - Hold violations may be seen on a path clocked by riu_clk N/A N/A
59948 UltraScale DDR4/DDR3 - Incorrect clock connection on dbg_hub which can have a negative timing impact. N/A N/A
61901 UltraScale DDR3/DDR4 - memory model violations observed during simulation N/A N/A
60181 UltraScale DDR4/DDR3 - Timing violations can occur at higher data rates N/A N/A
63022 UltraScale DDR4/DDR3 - Designs targeting dual rank DIMMs with address mirroring fail in hardware N/A N/A
64887 UltraScale DDR4/DDR3 -Tactical Patch - Errors occur when implementing a 2015.1 MIG (v7.0) IP in Vivado 2015.2 N/A N/A
64615 UltraScale DDR4/DDR3 - AXI Interface efficiency improvements for 2015.2 N/A N/A
66937 UltraScale/UltraScale+ DDR4 and DDR3 IP - UNISIM simulations fail when using Self Refresh and Self Restore options N/A N/A
66560 UltraScale/UltraScale+ DDR3 and DDR4 IP - IP Generation Fails when Custom Part CSV File is Loaded for Twin Die Component N/A N/A
71531 UltraScale/UltraScale+ DDR4 DDR3 Post Save Restore ECC 错误仅限多排 N/A N/A
71697 UltraScale+ RFSoC DDR4/DDR3/RLDRAM3 - The FSVE1156 package allows incorrect data widths N/A N/A
72789 UltraScale/UltraScale+ DDR3/DDR4 IP - Usage Guidelines for Multiple High Frequency Save/Restore Cycles N/A N/A
72582 UltraScale 内存 IP — 航天级 Kintex UltraScale XQRKU 060 器件字节规划器错误或 Bank 46 或 Bank 25 中的 MIG 66-99 错误 N/A N/A
69071 UltraScale/UltraScale+ DDR4/DDR3 IP - Simulations using UNISIM Models in NCSIM or Using the ncinitialize Switch Gives Unexpected Results N/A N/A
73052 UltraScale/UltraScale+ DDR3/DDR4 IP - [Mig 66-119] Phy Core Regeneration and Stitching Failed N/A N/A
73068 面向 UltraScale/UltraScale+ DDR4/DDR3 IP 的设计咨询 - 存储器 IP 时序异常可能导致校准后硬件中出现数据错误或 DQS 门控跟踪错误 N/A N/A
73714 UltraScale/UltraScale+ Memory IP - Locked IPs from Earlier Versions of Vivado when Brought in to 2020.1 or Later Will Encounter Errors During Implementation or in Hardware N/A N/A
73715 UltraScale/UltraScale+ DDR3/DDR4 IP - Locked IPs using Self-Refresh with RDIMMs Must be Upgraded to Vivado 2020.1 or Later when Brought in to Vivado 2020.1 and Later N/A N/A
AR# 69036
日期 06/10/2020
状态 Active
Type 发布说明
器件 More Less
Tools
IP