AR# 69038

UltraScale/UltraScale+ QDRII+ - Release Notes and Known Issues

描述

This answer record contains the Release Notes and Known Issues for the QDRII+ UltraScale and UltraScale+ cores and includes the following:

  • 通用信息
  • 已知和已解决的问题
  • 修订历史

This Release Notes and Known Issues Answer Record is for the programmable logic QDRII+ IP core supported in UltraScale and UltraScale+ based devices.

QDRII+ IP Page:



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整个 Xilinx 社区都可在这里提供帮助,您可提出问题并与 Xilinx 专家合作,以获得您需要的解决方案。

解决方案



支持的器件可在以下位置找到:

  • QDRII+ IP Page
  • 通过 Vivado
    • Open Vivado, go to the IP Catalog, right click on the QDRII+ IP, and then select Compatible Families

如欲查看新特性列表和所有版本添加的器件支持,请参见 Vivado 工具中提供该核的 Change Log 文件。

表 1 将内核版本关联至首个包含该表的 Vivado 设计工具发布版本。

表 1: 版本

Vivado 工具版本
2020.1
2019.2
2019.1
2018.3

2018.2
2018.1

2017.4

2017.3
2017.2
2017.1
2016.4
2016.3
2016.2
2016.1
2015.4
v1.02015.3
2015.2
v7.02015.1
v6.12014.4
v6.02014.3
2014.2
2014.1

如欲查看 UltraScale 系列 FPGA 的支持内存接口和工作频率列表,请访问存储器解决方案页面的外部存储器接口部分。

For a complete list of supported QDRII+ memory devices refer to the memory_device_support_qdrIIplus.xlsx attachment found at the bottom of this Answer Record.

已知和已解决的问题

Table 2 provides the known and resolved issues for the UltraScale family QDRII+ IP.

注:“发现问题的版本”栏列出了首次发现问题的版本。该问题可能也出现于较早版本,但未对较早版本进行特定测试。

表 2:已知问题和已解决问题

标题Version Found解决问题的版本
UltraScale/UltraScale+ Memory IP - Locked IPs from Earlier Versions of Vivado when Brought in to 2020.1 or Later Will Encounter Errors During Implementation or in HardwareNF
UltraScale/UltraScale+ QDRII+ IP - Byte 3 of a 36-bit QDRII+ Interface Not Showing Calibration Margins in the Hardware Managev1.2Will not be fixed
UltraScale/UltraScale+ QDRII+ IP - Are GSI memory models supported in simulation?v1.3 (Rev. 1)Not a bug
UltraScale/UltraScale+ QDRII+ IP — XSDB 报告的内存频率不正确v1.2 (Rev. 1)v1.4 (Rev. 6)
UltraScale/UltraScale+ QDRII+ IP - *_ooc.xdc constraints file does not get generated in Out-Of-Context (OOC) modev1.2 (Rev. 1)Will not be fixed
UltraScale/UltraScale+ QDRII+ IP - XSDB Debugger indicates MicroBlaze has failed but calibration completesv7.0v1.0
UltraScale/UltraScale+ QDRII+ IP - Core generation fails due to invalid Memory Device Interface Speed settingv7.0v7.1
UltraScale/UltraScale+ QDRII+ IP - Unexpected DRC for correct placement of memory clock pair (K/K#)v7.0v7.1
UltraScale/UltraScale+ QDRII+ IP - Read latency 2.0 (RL2) and Burst length 2 (BL2) designs fail simulation with Cypress memory modelv7.0v7.1
UltraScale/UltraScale+ QDRII+ IP - Calibration and intermittent data errors due to improper calibration resultsv6.1v7.0
UltraScale/UltraScale+ DDR3/DDR4/QDRII+ - Multi-driver errors found during LINT checkv6.1v7.0
面向 UltraScale/UltraScale+ QDRII+ IP 的设计咨询 – I/O Planner 未捕捉到管脚 DRC 违规v5.0 Rev1v6.0
UltraScale/UltraScale+ QDRII+ IP — Cypress 内存模型中的多驱动程序问题在仿真中导致数据错误v5.0 Rev1N/A
UltraScale/UltraScale+ RLDRAM3 and QDRII+ - Timing failure from XiPHY to riu_clkv5.0 Rev 1v6.0
UltraScale/UltraScale+ QDRII+ IP - Incorrect parameter values for 36-bit designs using x18 components
v5.0N/A


修订历史::


Created Separate Answer Record for QDRII+
Updated formatting
2017.4 更新
2018.1 更新

2018.3 更新
05/02/20192019.1 更新

2019.2 更新
2020.1 更新

附件

文件名 文件大小 File Type
memory_device_support_qdriiplus.xlsx 19 KB XLSX

链接问答记录

主要问答记录

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
68751 UltraScale/UltraScale+ QDRII+ IP - Are GSI memory models supported in simulation? N/A N/A
67959 UltraScale/UltraScale+ QDRII+ IP — XSDB 报告的内存频率不正确 N/A N/A
67336 UltraScale/UltraScale+ QDRII+ IP - *_ooc.xdc constraints file does not get generated in Out-Of-Context (OOC) mode N/A N/A
64783 UltraScale/UltraScale+ QDRII+ IP - XSDB Debugger indicates MicroBlaze has failed but calibration completes N/A N/A
64488 UltraScale/UltraScale+ QDRII+ IP - Core generation fails due to invalid Memory Device Interface Speed setting N/A N/A
64006 UltraScale/UltraScale+ QDRII+ IP - Unexpected DRC for correct placement of memory clock pair (K/K#) N/A N/A
64427 UltraScale/UltraScale+ QDRII+ IP - Calibration and intermittent data errors due to improper calibration results N/A N/A
62157 面向 UltraScale/UltraScale+ QDRII+ IP 的设计咨询 – I/O Planner 未捕捉到管脚 DRC 违规 N/A N/A
61555 UltraScale/UltraScale+ QDRII+ IP — Cypress 内存模型中的多驱动程序问题在仿真中导致数据错误 N/A N/A
60047 UltraScale/UltraScale+ QDRII+ IP - Incorrect parameter values for 36-bit designs using x18 components N/A N/A
63261 UltraScale DDR3/DDR4/QDRII+ - Multi-driver errors found during LINT check N/A N/A
60951 UltraScale RLDRAM3/QDRII+ - Timing failure from XiPHY to riu_clk N/A N/A
63689 UltraScale/UltraScale+ QDRII+ IP - Read Latency 2.0 (RL2) and Burst Length 2 (BL2) designs fail simulation with Cypress memory model N/A N/A
71400 UltraScale/UltraScale+ QDRII+ IP - Byte 3 of a 36-bit QDRII+ Interface Not Showing Calibration Margins in the Hardware Manager N/A N/A
73714 UltraScale/UltraScale+ Memory IP - Locked IPs from Earlier Versions of Vivado when Brought in to 2020.1 or Later Will Encounter Errors During Implementation or in Hardware N/A N/A
AR# 69038
日期 06/10/2020
状态 Active
Type 发布说明
器件 More Less
Tools
IP