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AR# 69038

UltraScale/UltraScale+ QDRII+ - Release Notes and Known Issues

描述

This answer record contains the Release Notes and Known Issues for the QDRII+ UltraScale and UltraScale+ cores and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the programmable logic QDRII+ IP core supported in UltraScale and UltraScale+ based devices.

QDRII+ IP Page:


https://www.xilinx.com/products/intellectual-property/qdrii-plus.html#overview


Xilinx Forums:

Please seek technical support via the Memory Interfaces Board. The Xilinx Forums are a great resource for technical support. 

The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.

解决方案

General Information

Supported devices can be found in the following locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

QDRII+ VersionVivado Tools Version
v1.4 (Rev. 7)2019.1
v1.4 (Rev. 6)2018.3
v1.4 (Rev. 5)
2018.2
v1.4 (Rev. 4)2018.1
v1.4 (Rev. 3)
2017.4
v1.4 (Rev. 2)
2017.3
v1.4 (Rev. 1)2017.2
v1.42017.1
v1.3 (Rev. 1)2016.4
v1.32016.3
v1.2 (Rev. 1)2016.2
v1.22016.1
v1.12015.4
v1.02015.3
v7.12015.2
v7.02015.1
v6.12014.4
v6.02014.3
v5.0 Rev12014.2
v5.02014.1

For a list of supported memory interfaces and operating frequencies for UltraScale family FPGAs go to the External Memory Interfaces section of the Memory Solutions page:

https://www.xilinx.com/products/technology/memory.html#externalMemory

For a complete list of supported QDRII+ memory devices refer to the memory_device_support_qdrIIplus.xlsx attachment found at the bottom of this Answer Record.

For the latest info on what is new for Vivado, including supported operating systems and IP release notes, see (UG973).

Known and Resolved Issues

Table 2 provides the known and resolved issues for the UltraScale family QDRII+ IP.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Table 2: Known and Resolved Issues

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 71400)UltraScale/UltraScale+ QDRII+ IP - Byte 3 of a 36-bit QDRII+ Interface Not Showing Calibration Margins in the Hardware Managev1.2Will not be fixed
(Xilinx Answer 68751)UltraScale/UltraScale+ QDRII+ IP - Are GSI memory models supported in simulation?v1.3 (Rev. 1)Not a bug
(Xilinx Answer 67959)UltraScale/UltraScale+ QDRII+ IP - XSDB reports Memory Frequency incorrectlyv1.2 (Rev. 1)v1.4 (Rev. 6)
(Xilinx Answer 67336)UltraScale/UltraScale+ QDRII+ IP - *_ooc.xdc constraints file does not get generated in Out-Of-Context (OOC) modev1.2 (Rev. 1)Will not be fixed
(Xilinx Answer 64783)UltraScale/UltraScale+ QDRII+ IP - XSDB Debugger indicates MicroBlaze has failed but calibration completesv7.0v1.0
(Xilinx Answer 64488)UltraScale/UltraScale+ QDRII+ IP - Core generation fails due to invalid Memory Device Interface Speed settingv7.0v7.1
(Xilinx Answer 64006)UltraScale/UltraScale+ QDRII+ IP - Unexpected DRC for correct placement of memory clock pair (K/K#)v7.0v7.1
(Xilinx Answer 63689)UltraScale/UltraScale+ QDRII+ IP - Read latency 2.0 (RL2) and Burst length 2 (BL2) designs fail simulation with Cypress memory modelv7.0v7.1
(Xilinx Answer 64427)UltraScale/UltraScale+ QDRII+ IP - Calibration and intermittent data errors due to improper calibration resultsv6.1v7.0
(Xilinx Answer 63261) UltraScale/UltraScale+ DDR3/DDR4/QDRII+ - Multi-driver errors found during LINT checkv6.1v7.0
(Xilinx Answer 62157)Design Advisory for UltraScale/UltraScale+ QDRII+ IP - Pinout DRC violations not caught in I/O Plannerv5.0 Rev1v6.0
(Xilinx Answer 61555)UltraScale/UltraScale+ QDRII+ IP - Multi-driver issue in Cypress memory model causes data errors in simulationv5.0 Rev1N/A
(Xilinx Answer 60951)UltraScale/UltraScale+ RLDRAM3 and QDRII+ - Timing failure from XiPHY to riu_clkv5.0 Rev 1v6.0
(Xilinx Answer 60047)UltraScale/UltraScale+ QDRII+ IP - Incorrect parameter values for 36-bit designs using x18 components
v5.0N/A


Revision History:


04/18/2017Created Separate Answer Record for QDRII+
06/12/2017Updated for 2017.2; Added (Xilinx Answer 68028), (Xilinx Answer 69291)
06/22/2017Added (Xilinx Answer 69324)
07/31/2017Updated debugging link to (Xilinx Answer 68937)
09/18/2017Updated formatting
12/12/2017Updated for 2017.4
03/13/2018Updated for 2018.1
08/02/2018Added (Xilinx Answer 71400), Updated for 2018.2
09/20/2018Updated for 2018.3
05/02/2019Updated for 2019.1

附件

文件名 文件大小 File Type
memory_device_support_qdriiplus.xlsx 16 KB XLSX

链接问答记录

主要问答记录

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
68751 UltraScale/UltraScale+ QDRII+ IP - Are GSI memory models supported in simulation? N/A N/A
67959 UltraScale/UltraScale+ QDRII+ IP — XSDB 报告的内存频率不正确 N/A N/A
67336 UltraScale/UltraScale+ QDRII+ IP - *_ooc.xdc constraints file does not get generated in Out-Of-Context (OOC) mode N/A N/A
64783 UltraScale/UltraScale+ QDRII+ IP - XSDB Debugger indicates MicroBlaze has failed but calibration completes N/A N/A
64488 UltraScale/UltraScale+ QDRII+ IP - Core generation fails due to invalid Memory Device Interface Speed setting N/A N/A
64006 UltraScale/UltraScale+ QDRII+ IP - Unexpected DRC for correct placement of memory clock pair (K/K#) N/A N/A
64427 UltraScale/UltraScale+ QDRII+ IP - Calibration and intermittent data errors due to improper calibration results N/A N/A
62157 面向 UltraScale/UltraScale+ QDRII+ IP 的设计咨询 – I/O Planner 未捕捉到管脚 DRC 违规 N/A N/A
61555 UltraScale/UltraScale+ QDRII+ IP — Cypress 内存模型中的多驱动程序问题在仿真中导致数据错误 N/A N/A
60047 UltraScale/UltraScale+ QDRII+ IP - Incorrect parameter values for 36-bit designs using x18 components N/A N/A
63261 UltraScale DDR3/DDR4/QDRII+ - Multi-driver errors found during LINT check N/A N/A
60951 UltraScale RLDRAM3/QDRII+ - Timing failure from XiPHY to riu_clk N/A N/A
63689 UltraScale/UltraScale+ QDRII+ IP - Read Latency 2.0 (RL2) and Burst Length 2 (BL2) designs fail simulation with Cypress memory model N/A N/A
71400 UltraScale/UltraScale+ QDRII+ IP - Byte 3 of a 36-bit QDRII+ Interface Not Showing Calibration Margins in the Hardware Manager N/A N/A
AR# 69038
日期 05/29/2019
状态 Active
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