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AR# 69040

UltraScale/UltraScale+ LPDDR3 IP - Release Notes and Known Issues


This answer record contains the Release Notes and Known Issues for the LPDDR3 UltraScale and UltraScale+ cores and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the programmable logic LPDDR3 IP core supported in UltraScale and UltraScale+ based devices.



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General Information

Supported devices can be found in the following locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

LPDDR3 VersionVivado Tools Version
v1.0 (Rev. 8)2019.2
v1.0 (Rev. 7) 2019.1
v1.0 (Rev. 6)2018.3
v1.0 (Rev. 5)2018.2
v1.0 (Rev. 4)
v1.0 (Rev. 3)2017.4
v1.0 (Rev. 2)2017.3
v1.0 (Rev. 1)2017.2

For a list of supported memory interfaces and operating frequencies for UltraScale family FPGAs go to the External Memory Interfaces section of the Memory Solutions page:


For a complete list of supported LPDDR3 memory devices, refer to the memory_device_support_lpddr3.xlsx attachment found at the bottom of this Answer Record.

For the latest info on what is new for Vivado, including supported operating systems and IP release notes, see (UG973).

Known and Resolved Issues

Table 2 provides the known and resolved issues for the UltraScale family LPDDR3 IP.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Table 2: Known and Resolved Issues

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 69436)UltraScale/UltraScale+ LPDDR3 IP - Mode Register Settings v1.0NAB
(Xilinx Answer 69435)UltraScale/UltraScale+ LPDDR3 IP - PCBA Layout Guidelines v1.0NAB
(Xilinx Answer 69282)UltraScale/UltraScale+ LPDDR3 IP - DRC Warning [DRC BIIVRC-1] from Bank INTERNAL_VREF Constraint Conflict with I/O Standard Vref v1.0NAB
(Xilinx Answer 69141)UltraScale/UltraScale+ LPDDR3 IP - Memory Model Simulation Errors for QuestaSim and Other Simulatorsv1.0NAB
(Xilinx Answer 69041)UltraScale/UltraScale+ LPDDR3  IP - Non-Supported Frequencies (Greater than 533MHz) Allowed in High Range I/O Banks v1.0v1.0 (Rev. 1)
(Xilinx Answer 69029)UltraScale/UltraScale+ LPDDR3 IP - Output Impedance DRC Violations when using High Range Banks with Kintex UltraScale Devices v1.0v1.0 (Rev. 1)
(Xilinx Answer 69028)UltraScale/UltraScale+ LPDDR3 IP - Automatic Byte-Planner Error when Using High Range Banks in Kintex UltraScale Devicesv1.0v1.0 (Rev. 1)

Revision History:

04/18/2017Created Separate Answer Record for LPDDR3
05/03/2017Added AR69141
06/12/2017Updated for 2017.2, Added AR69291
06/22/2017Added AR69324
07/05/2017Added AR69435 and AR69436
08/31/2017Removed generic AR link and updated AR formatting
09/18/2017Updated for 2017.3
12/12/2017Updated for 2017.4
03/13/2018Updated for 2018.1
09/20/2018Updated for 2018.3
05/02/2019Updated for 2019.1
10/20/2019Updated for 2019.2


文件名 文件大小 File Type
memory_device_support_lpddr3.xlsx 16 KB XLSX



Answer Number 问答标题 问题版本 已解决问题的版本
58435 UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues N/A N/A


AR# 69040
日期 10/24/2019
状态 Active
Type 版本说明
器件 More Less