AR# 69044


Dual-purpose I2C pins used as output ports do not have correct signal output


UltraScale FPGAs have a pair of dual-purpose pins for the I2C port of the SYSMONE1 that can also be used as I/O ports in the design.

After power-on, these two pins behave like they are always in 3-state mode.

The design logic and I/O settings do not cause any errors or warnings during synthesis or implementation.

What can cause this issue?


This is can happen when there is a conflict between the SYSMONE1 I2C settings and the I/O placement.

If the SYSMONE1 primitive is instantiated in the design and Bit 7 of register 43H in SYSMON is set to 1, it enables these dual-purpose I2C pins, which disables those pins from being used as I/O.

From (UG580):



You can read the register with this command:

[get_hw_sysmon_reg [lindex [get_hw_sysmons] 0 ] 43 ]

To resolve this issue, modify the INIT_43 attribute of SYSMON instantiation so that its bit 7 is set to 0.

Note: this can only happen when the SYSMONE1 is manually instantiated.

The System Management wizard inserts the I/O buffers for the I2C ports into the netlist so the tools will not allow I/Os to be placed at these sites.

A DRC will be added to an upcoming release of the tools to check that the I2C pins are not assigned to user I/O when the I2C_EN bit is set on the SYSMONE1.

AR# 69044
日期 04/28/2017
状态 Active
Type 综合文章
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