AR# 69071

UltraScale/UltraScale+ DDR4/DDR3 IP - Simulations using UNISIM Models in NCSIM or Using the ncinitialize Switch Gives Unexpected Results


Version Found: DDR4 v2.1 (Rev. 1) and DDR3 v1.3 (Rev. 1)

Version Resolved: See (Xilinx Answer 69035) for DDR4 and (Xilinx Answer 69036) for DDR3

When running simulations of a DDR3/DDR4 interface using Cadence NCSIM or IES, if the Xilinx UNISIM model is selected in the IP and the ncinitialize switch is used in the simulation test bench, the results might not be as expected:

  • The write data and read data might be correct when looking at the memory interface in the simulation but the data errors can appear at the top level user interface of the IP.
  • Sometimes the read data can be all zeros even though the written data was a non zero value.
  • In other cases the AXI read channel can generate the correct number of RVALID but the Read Data is misaligned or stale.
  • When digging in to the IP the valid and data get unaligned at the UI to AXI boundary.

Note: this issue can happen with native as well as AXI interfaces.


Using the ncinitialize switch causes a problem with the Micron memory model as it leads to unknown values in the simulation test bench.

If you are experiencing any strange simulation issues with NCSIM then check if you are using ncinitialize in your test bench.


Using ncinitialize 0 causes problems with the Xilinx XIPHY UNISIM model.

Micron and Xilinx are aware of this behavior but it is not planned to be fixed.

There are two work-arounds available:


  1. Do not use the ncinitialize switch
  2. If the ncinitialize must be used then set ncinitialize to 0 and generate the DDR3/DDR4 IP with the BFM model selected instead of the UNISIM model from the Advanced options tab




Answer Number 问答标题 问题版本 已解决问题的版本
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
AR# 69071
日期 03/29/2020
状态 Active
Type 已知问题
器件 More Less