Version Found: DDR4 v2.1 (Rev. 1) and DDR3 v1.3 (Rev. 1)
When running simulations of a DDR3/DDR4 interface using Cadence NCSIM or IES, if the Xilinx UNISIM model is selected in the IP and the ncinitialize switch is used in the simulation test bench, the results might not be as expected:
Note: this issue can happen with native as well as AXI interfaces.
Using the ncinitialize switch causes a problem with the Micron memory model as it leads to unknown values in the simulation test bench.
If you are experiencing any strange simulation issues with NCSIM then check if you are using ncinitialize in your test bench.
Using ncinitialize 0 causes problems with the Xilinx XIPHY UNISIM model.
Micron and Xilinx are aware of this behavior but it is not planned to be fixed.
There are two work-arounds available: