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AR# 69221

Zynq UltraScale+ MPSoC - Debug

描述

This answer record lists the Zynq UltraScale+ MPSoC answer records related to the debug solutions available, including debug guides and how to set up third-party debugging tools.

Note: This article is part of Xilinx Zynq UltraScale+ MPSoC Solution Center (Xilinx Answer 64375).

The Xilinx Zynq UltraScale+ MPSoC Solution Center is available to address all questions related to Zynq UltraScale+ MPSoC. 

Whether you are starting a new design or troubleshooting a problem, use the Solution Center to guide you to the right information.

解决方案

General Zynq UltraScale+ MPSoC Debug Setup Answer Records

(Xilinx Answer 67356) Zynq UltraScale+ MPSoC: How to connect the JTAG signal of a Mictor (TRACE) connector
(Xilinx Answer 67871) Zynq UltraScale+ MPSoC: MicroBlaze PMU MDM is disabled by default on ES2 and higher. 
(Xilinx Answer 68391) Zynq UltraScale+ MPSoC: booting in secure mode, how do I enable JTAG?
(Xilinx Answer 67818) Zynq UltraScale+ MPSoC: 2016.3 PMUFW Loading via JTAG / SD Boot Modes and Running An Example

Third-party Debug Tools Answer Records

(Xilinx Answer 68662) Zynq UltraScale+ MPSoC - What are the debugger solutions and tests done with JTAG/TRACE/PJTAG interfaces?

Xilinx Tools Answer Records

Xilinx Answer TitleTool Version FoundTool Version Resolved
(Xilinx Answer 67740)Zynq UltraScale+ MPSoC - XSDB (or any other JTAG user) needs to hold the TMS signal high for 5 TCK cycles to enable PL TAP linking to the JTAG chain. 2016.22016.3
(Xilinx Answer 68439)Zynq UltraScale - PL MicroBlaze is not detected in the XSDB 2016.2N.A.
(Xilinx Answer 66436)Zynq UltraScale+ MPSoC - XSDB is not able to connect to PSU after successfully booting in SD mode on ZCU1022016.12016.3
(Xilinx Answer 67145)Zynq UltraScale+ MPSoC, Vivado 2016.1 - ILA/IBA cores are not found in Vivado Hardware Manager for ZU3 and ZU15 devices 2016.12016.2
 

Zynq UltraScale+ MPSoC Boards Debug Answer Records

(Xilinx Answer 68386) Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit - Board Debug Checklist
(Xilinx Answer 69244) Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit Interface Test Designs

 

Related Documentation

Zynq- UltraScale+ MPSoC Technical Reference Manual UG1085:

Chapter 39: System Test and Debug

Useful Links

For the initialization script to run on TRACE32 to connect to the Zynq processors (http://www.lauterbach.com/scripts.html).

For more information on ARM DS-5 (www.arm.com/ds5).

AR# 69221
日期 06/07/2017
状态 Active
Type 解决方案中心
器件
的页面