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AR# 69227

LogiCORE IP Video Timing Controller v6.1 - How do I configure the Video Timing Controller to de-assert VBLANK at the same time as the HBLANK at the end of the last line of the frame?

描述

How do I configure the Video Timing Controller to de-assert VBLANK at the same time as the HBLANK at the end of the last line of the frame?

解决方案

Setting VBLANK to de-assert at the same time as HBLANK on the last line of the frame is not supported.

The way that the settings for the Video Timing Controller work is that the user defines the active region (H Active, V Active Size) and the full frame size (H Frame Size, V Frame Size).

Based on this, the IP will extrapolate the blank timing.

  • HBLANK is always at the end of a line
  • VBLANK is always at the end of a frame

The controls available to the user are (GENERATOR F0_VBLANK_H - 0x007C):

  • Vblank Start (F0_VBLANK_HSTART) - The horizontal pixel location during the last ACTIVE line when VBLANK will be asserted
  • Vblank End (F0_VBLANK_HEND) - The horizontal pixel location during the last FRAME line when the VBLANK will be de-asserted

The typical use case is for VBLANK to de-assert at the same time HBLANK asserts. However, the closest possible configuration to this is still off by 1 clock cycle.

You can configure the VBLANK to de-assert one clock cycle before HBLANK de-asserts on the last line of the frame. This is done by setting the Vblank End (F0_VBLANK_HEND) = HFRAME_SIZE - 1.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54541 LogiCORE IP Video Timing Controller - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 69227
日期 06/07/2017
状态 Active
Type 综合文章
IP
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