This Xilinx Answer describes the required step to demonstrate booting a Zynq UltraScale+ MPSoC device in QSPI execute-in-place (XIP) on a ZCU102
This is NOT a full solution but a starting point to touch on a few useful concepts when working on XIP with Zynq UltraScale+ MPSoC.
Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq devices.
A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools.
It is the users responsibility to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill his needs.
Limited support is provided by Xilinx on these Example Designs.
|Design Type||PS Only|
|PS Features||QSPI in Linear mode|
|Xilinx Tools Version||2017.2 (There is a bug in 2017.1 bootgen regarding xip_mode for A53)|
Create a Vivado project for ZCU102, Run Block Automation on the Processing System IP and then customize the QSPI interface to be "Single".
Note: Execute-in-place is ONLY SUPPORTED for QSPI in Single Configuration.
Generate the Block Design, Create the HDl Wrapper and Export HW to XSDK.
Create an Empty Application. In this example we will call it "mpsoc_qspi_xip".
Import the attached files.
Note: XSDK will ask to overwrite the linker script: Press "Yes".
Use the following .bif file to generate the bootable BOOT.bin
bootgen -arch zynqmp -image output.bif -o BOOT.bin -w
Using the bootgen_utility command you can decode the generated BOOT.bin in text format and study how the flag "xip_mode" impacted the image header.
(bootgen_utility -arch zynqmp -bin BOOT.bin
See (UG1137) for more details.
Note: 2017.1 bootgen has an issue where xip_mode generates the proper ARM Vector Table in the image ONLY for R5 and A53-32bit.
Below is a snippet for A53-64bit from the 2017.2 version: