AR# 69272


2017.3 Zynq UltraScale+ MPSoC - DBG_TRACE clock attribute must match pl_ps_trace_clk frequency


When routing the TRACE port over EMIO the user must provide an input clock to the pl_ps_trace_clk signal.

For proper operation the frequency of this clock MUST match the value of DBG_TRACE.

Note: In most cases, pl_ps_trace_clk is fed by one of the pl_clk clocks.


A CRITICAL WARNING has been added in 2017.3 Vivado to avoid improper configurations.


The possible work-arounds are:

  • Change the DBG_TRACE input value to be pl_ps_trace_clk * 2
  • Change the value of the clock feeding pl_ps_trace_clk to DBG_TRACE / 2.
AR# 69272
日期 12/20/2017
状态 Active
Type 综合文章
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