AR# 69276

Zynq UltraScale+ MPSoC - PS SPI routed through EMIO, read data is always 0

描述

On my Zynq UltraScale+ device, the PS is SPI configured to route through EMIO in the PL logic if the user sets ss_i to 1, to force it to master mode only.

The firmware driver uses it as a master only.

I see the correct MOSI data coming out of the Zynq device, and the correct MISO data going back to the Zynq device.

I have connected the Zynq internal SPI bus signals in the PL to pins, and can see the correct MISO data on the pins. 

However, when the driver reads the RX data, it always reads 0x00s only.

When I enable SPI via EMIO in Zynq UltraScale+, I can see that there are twelve pins under the SPI interface. 

Which pins should be used for SPI transactions?


 

解决方案

You might not require all of the signals under EMIO SPI_0 or SPI_1 when you route through EMIO. 

This is mostly a topology issue. 

The following signals need to be made external:

  1. emio_spi0_m_o   -> MOSI
  2. emio_spi0_m_i    ->  MISO
  3. emio_spi0_sclk_o -> CLK
  4. emio_spi0_ss_o_n -> SS


The design should look like the following once you set these signals as external pins instead of PS SPI:


 

Please note that the design recommendation works and there is no need to tie the PS SPI ss_i pin to high when used in master mode.

The issue is seen in Vivado versions up to 2018.3, and should be fixed in a future version.

AR# 69276
日期 11/08/2018
状态 Active
Type 综合文章
器件
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