Version Found: MIG 7 Series v3.0
Version Resolved: See (Xilinx Answer 54025)When adding the Memory Interface Generator (MIG 7 Series) IP to a Spartan-7 or Artix-7 based design you will see a notification message underneath the Clock Period field in the Controller Options of the MIG GUI:
In order to make the most efficient use of Artix-7 and Spartan-7 device resources, the MIG IP was optimized for certain controller options for LPDDR2, DDR3, and DDR3L based interfaces.
The interface rate is optimized up to 667Mbp/s (333MHz) and operating at higher data rates will cause a comparatively large increase in resource utilization.
Devices with a maximum memory interface clock rate less than 333MHz can operate up to their maximum value without any additional penalty.
The MIG IP is also optimized for component interfaces, a 2:1 PHY to controller clock ratio, strict command ordering, and the number of bank machines on a per device basis.
Using the default settings in the Controller Options page of the MIG customization GUI typically results in a 30% LUT saving when compared to designs that do not use the default settings.
08/02/2017 - Initial Release