Version Found: LPDDR3 v1.0
Version Resolved: See (Xilinx Answer 69040)
The PCBA layout guidelines for LPDDR3 memory interfaces for both the PS and PL of UltraScale and UltraScale+ FPGA and MPSoC devices can be found in (UG583)
The complete PCBA layout guidelines for LPDDR3 interfaces in either the programmable logic soft controllers or the hardened PS DDR controller in Zynq MPSoC devices can be found in (UG583)
|02/26/2018||Updated Clock to Address/Command/Control midrange from +/- 8ps to +/-4ps and +/- 47mil to +/-23mil.|
|12/04/2019||Updated AR to reference UG583 as all the LPDDR3 PCBA layout guidelines are now documented there.