AR# 69435


UltraScale/UltraScale+ LPDDR3 IP - PCBA Layout Guidelines


Version Found: LPDDR3 v1.0

Version Resolved: See (Xilinx Answer 69040)

The PCBA layout guidelines for LPDDR3 memory interfaces for both the PS and PL of UltraScale and UltraScale+ FPGA and MPSoC devices can be found in (UG583)


The complete PCBA layout guidelines for LPDDR3 interfaces in either the programmable logic soft controllers or the hardened PS DDR controller in Zynq MPSoC devices can be found in (UG583)

Revision History:

07/05/2017 Initial Release
09/18/2017 Updated constraints
02/26/2018 Updated Clock to Address/Command/Control midrange from +/- 8ps to +/-4ps and +/- 47mil to +/-23mil.
12/04/2019 Updated AR to reference UG583 as all the LPDDR3 PCBA layout guidelines are now documented there.



Answer Number 问答标题 问题版本 已解决问题的版本
69040 UltraScale/UltraScale+ LPDDR3 IP - Release Notes and Known Issues N/A N/A
AR# 69435
日期 01/06/2020
状态 Active
Type 综合文章
器件 More Less
People Also Viewed