AR# 69436


UltraScale/UltraScale+ LPDDR3 IP - Mode Register Settings


Version Found: LPDDR3 v1.0

Version Resolved: See (Xilinx Answer 69040)

Unlike previous programmable logic UltraScale memory interface IPs, the LPDDR3 mode register values are mostly hidden in the design and cannot be easily derived from the files.


All other mode registers not mentioned in this Answer Record are left at their default values, and the design does not support modification of these values.

The LPDDR3 IP only has native support for the MT52L256M32D1PF-107 Micron memory device, so that will be used for generating the data sheet timing parameters.

  • MR1 always uses BL=8 and the nWR is derived from the Micron data sheet values and the LPDDR3 interface clock rate.
  • MR2 generates the "RL and WL" and nWRE values from the Micron data sheet values and the LPDDR3 interface clock rate.
  • MR3 is always set to 0x2 for 40-ohm pull-up and pull-down drive strength.
  • MR10 is only used for ZQ Calibration at initialization.
    The IP does not issue periodic ZQ Calibration Short (ZQCS) commands because testing showed no improvement in SI or timing in the single rank point-to-point interface the IP supports.
  • MR11 is always set to 0x2 for RZQ/2 DQ ODT.

Revision History

07/28/2017 - Initial Release

02/15/2018 - Fixed typo in MR3 definition - MR3 is set to 0x2 and not 0xA



Answer Number 问答标题 问题版本 已解决问题的版本
69040 UltraScale/UltraScale+ LPDDR3 IP - Release Notes and Known Issues N/A N/A
AR# 69436
日期 02/27/2018
状态 Active
Type 综合文章
器件 More Less
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