Version Found: LPDDR3 v1.0
Version Resolved: See (Xilinx Answer 69040)
Unlike previous programmable logic UltraScale memory interface IPs, the LPDDR3 mode register values are mostly hidden in the design and cannot be easily derived from the files.
All other mode registers not mentioned in this Answer Record are left at their default values, and the design does not support modification of these values.
The LPDDR3 IP only has native support for the MT52L256M32D1PF-107 Micron memory device, so that will be used for generating the data sheet timing parameters.
07/28/2017 - Initial Release
02/15/2018 - Fixed typo in MR3 definition - MR3 is set to 0x2 and not 0xA