The System MMU (SMMU) in the Zynq UltraScale+ MPSoC PS uses 15-bit StreamIDs to designate which master has access to memory.
The StreamID bits for PL masters connected to the HP and HPC ports are derived as follows:
SmartConnect does not provide AWID/ARID to the PL.
The SMMU has no way to distinguish between two masters connected to the same HP ports.
This means that Master A could access Master B's memory region.
One situation where this can be a problem is when running applications on a hypervisor like Xen.
Master A associated with application A should not have access to the memory resources allocated for Master B associated with application B.
Releases prior to 2018.1:
The work-around is to not use SmartConnect, instead replace it with the AXI Interconnect.
AXI Interconnect prepends a "Master ID" value to the incoming AWID/ARID signals that is based on the SI-slot number.
This creates a unique ID for the PL masters that share a HP or HPC port.
Alternatively, consider connecting to separate PL AXI interfaces which will also be prepended with separate AXI IDs internal to the PS.
2018.1 and later releases:
The AXI Sideband Format Utility IP enforces unique IDs through the SmartConnect IP.
The IP performs SMID insertion and extraction on the AxUSER bits to ensure that the IDs can pass through SmartConnect.
This IP was introduced in the 2018.1 release of Vivado and is the recommended approach to use for new designs.
For details, please refer to (PG307).
A Tcl script to generate an example block diagram is attached. It was created in the 2018.1 version, and shows how to include the AXI Sideband Format Utility IP in an MPSoC design where multiple AXI CDMA IPs connect to the S_AXI_HP0_FPD.
The table below shows the full SMID for axi_cdma_0 and axi_cdma_1.
The TCU and Master ID fields are described in Chapter 16 of (UG1085).
The full SMID is necessary to configure the SMMU.
|IP||TBU ID[14:10]||Master ID[9:6]||AXI ID[5:0]||Stream ID[14:0]|
15'b000_1110_1000_0000 = 15'h0E80
|axi_cdma_1||5'b0_0011||4'b1010||6'b00_0001||15'b000_1110_1000_0001 = 15'h0E81|
The block diagram showing only the AXI interfaces is show below.
|Boards & Kits||