UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 69478

Design Advisory for UltraScale+ Families Master Answer Record

描述

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Design Advisory covers the Kintex UltraScale+ and Virtex UltraScale+ families.

解决方案

Design Advisory Alerted on August 13th, 2018

(Xilinx Answer 71371)Design Advisory for UltraScale+ GTH GTY I, M and Q grade - Data errors are occasionally seen on extreme temperature ramps


Design Advisory Alerted on June 19th, 2017

(Xilinx Answer 69152)Design Advisory 2017.1 Tactical Patch for Vivado bi-directional logic issue using component mode primitives (IOBUF usage with IDDRE1, ISERDESE3, ODDRE1, OSERDESE3, or FDCE/FDPE/FDRE/FDSE with IOB=TRUE)
 
Design Advisories Alerted on April 17th, 2017
(Xilinx Answer 69034)
Design Advisory for 7 Series, UltraScale and UltraScale+, all versions of Vivado prior to 2016.3 failed to include Flight time delays for differential I/O Standards
 
Design Advisories Alerted on April 10th, 2017
(Xilinx Answer 68832)Design Advisory for UltraScale FPGA, UltraScale+ FPGA, and Zynq UltraScale+ MPSoC eFUSE Programming with Vivado 2016.4 (and earlier) [SECURITY]

Design Advisory Alerted on December 19th, 2016
(Xilinx Answer 67645)Design Advisory for 7 Series and UltraScale Architecture FPGA configuration fallback and POST_CRC limitation [SECURITY]

链接问答记录

子答复记录

AR# 69478
日期 08/16/2019
状态 Active
Type 设计咨询
器件
的页面