How do I bring up the PHY on the Virtex UltraScale+ FPGA VCU118 Evaluation Kit and the Kintex UltraScale+ FPGA KCU116 Evaluation Kit?
In the VCU118 and KCU116 kits, the MGT Clock is driven from the TI PHY device DP83867ISRGZ.
The SGMII clock needs to be enabled, by writing 0x4000 to register 0xD3.
In the Control Register (Register 0), Enable Auto-negotiation and configure link speed and duplex settings.
In the Configuration Register 2 (CFG2), Address 0x0014, Configure interrupt polarity, enable auto negotiation, Enable Speed Optimization.
RGMII must be disabled, by writing 0cx0 to register 0x32.
Then wait for Link up by reading the link partner ability register (Register 5) poll for bit 14 to be set.
If RX_CTRL is not strapped to mode 3 or 4, a software work-around sequence is needed:
In Register 31, clear Bit 7 and set Bit 8 and bits [6:5]
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