AR# 69510

JESD204 PHY (v2.0) - CPLL_PD values incorrect if CPLL is not used and AXI-Lite is not enabled


When using the JESD204 PHY (v2.0) or later, if the CPLL is not used (both TX and RX are set to use QPLL) and the AXI-Lite interface is not enabled, CPLL_PD is set to 1 for lane 1 only and set to 0 for all other lanes.

This will result in the CPLLs for all lanes except lane 1 remaining powered up.

This will not affect the functionality of the design but it will result in the design using slightly more current than necessary.


To work around this issue, simply enable the AXI-Lite management interface on the JESD204 PHY.

In this way, the CPLL_PD bits will be driven by the AXI register interface logic which has the correct default values.

This will be resolved in Vivado 2017.3 version of the JESD204 PHY (v4.0).



Answer Number 问答标题 问题版本 已解决问题的版本
61911 LogiCORE IP JESD204 PHY 核 - 发布说明与已知问题 N/A N/A
AR# 69510
日期 07/26/2017
状态 Active
Type 综合文章