描述

When using the JESD204 PHY (v2.0) or later, if the CPLL is not used (both TX and RX are set to use QPLL) and the AXI-Lite interface is not enabled, CPLL_PD is set to 1 for lane 1 only and set to 0 for all other lanes.

This will result in the CPLLs for all lanes except lane 1 remaining powered up.

This will not affect the functionality of the design but it will result in the design using slightly more current than necessary.

解决方案

To work around this issue, simply enable the AXI-Lite management interface on the JESD204 PHY.

In this way, the CPLL_PD bits will be driven by the AXI register interface logic which has the correct default values.

This will be resolved in Vivado 2017.3 version of the JESD204 PHY (v4.0).

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