How much margin is there in the D-PHY RX (or MIPI CSI-2 RX Subsystem) line rate settings?
Xilinx cannot give an exact margin number and highly recommends that users set the correct line-rate in the MIPI D-PHY RX GUI when configuring the IP.
Based on the MIPI D-PHY RX IP, the user should be able to see the following results when the line rate is set at the below rates:
Please keep in mind that these are only estimates and have not been tested or verified.
The recommended solution is to select the correct line-rate when generating the MIPI D-PHY RX in the IP GUI.