AR# 69573


UltraScale/UltraScale+ DDR4 IP - 2017.x multi-controller designs fail calibration at WRITE_DQS_TO_DQ (complex) - IBUF_LOW_PWR attribute (2016.4 upgrade)


Version Found: DDR4 v2.2

Version Resolved: See (Xilinx Answer 69035)

It has been found that some designs that worked in 2016.x failed to calibrate after an upgrade to 2017.x

In each case there have been multiple memory controllers in the design. In rare instances it is possible for a single controller to calibrate after the upgrade but the rest do not. 

After an upgrade from 2016.4 to 2017.1 is the most common scenario for this error to surface.

Additional symptoms include the hardware manager reporting the memory IP as an "invalid core" or a calibration failure during WRITE_DQS_TO_DQ(COMPLEX), in addition to all speeds above 1600 failing calibration.


Note this behavior has only been observed in DDR4 multi-controller designs. 

It is possible that the same behavior will be observed with any memory controller operating above 1600Mbps.


All DDR4 interfaces should have the DQ, DM_DIB_N, and DQS buses set to IBUF_LOW_PWR FALSE.

This must be done post place-and-route.

First open the post place-and-route DCP (open implemented design) and then run the following commands for each DDR4 interface.

set_property IBUF_LOW_PWR FALSE [get_ports {c0_ddr4_dm_dbi_n[*]}]
set_property IBUF_LOW_PWR FALSE [get_ports {c0_ddr4_dq[*]}]
set_property IBUF_LOW_PWR FALSE [get_ports {c0_ddr4_dqs_*]



AR# 69573
日期 12/22/2017
状态 Active
Type 已知问题
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