What problems might be encountered if you exceed the maximum Tccl (CCLK low time) of 5.0 microseconds on some cycles when configuring a 3K device in Slave Serial mode?
Some of the configuration control logic is quasi-static. At higher temperatures the register contents of this logic can be lost if
the time between high levels of CCLK is too long, causing the associated state machine to become stuck in an invalid state.
To recover from this issue, power-down the device or cycle DONE and RESET.