AR# 69607


SDK 2017.2 - System Debugger does not have access to PL address regions on Zynq UltraScale+ MPSoC


In SDK 2017.2, the system debugger does not have access to the PL memory range. 

This issue can be manifested in the following ways:

  • XSDB/XSCT mrd/mwr command cannot access PL memory range addresses

xsct% Memory read error at 0xA0000000. Access can hang PS interconnect

  • SDK memory window cannot access those addresses (output ????????)


  • ZCU102 SPM project cannot configure ATG traffic:

10:51:52 ERROR : Unexpected error occurred while trying to configure ATG traffic for 'Performance_Analysis_On_ZynqMP'. Reason:Memory write error at 0xA0500000. PL AXI slave ports access is not allowed


In the SDK 2017.2 release, the "loadhw" command run by XSDB does not set the memory map correctly for Zynq UltraScale+ MPSoC devices, so accesses to the PL address ranges are blocked by the tool. 

The issue can be solved by applying the attached patch.

  • Unzip the patch in a local folder


  • Set the MYVIVADO environmental variable in your system (With the path pointing to where the script folder is located)


  • Launch SDK and check that the patch location has been identified by the tool:



文件名 文件大小 File Type 162 KB ZIP
AR# 69607
日期 08/18/2017
状态 Active
Type 综合文章
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