AR# 69670

Zynq UltraScale+ MPSoC - What is the behavior of the PS I/Os pre-configuration

描述

What is the behavior of the PS I/Os pre-configuration on a Zynq UltraScale+ MPSoC?

解决方案

When the PS_POR_B is asserted the default configuration registers of the PS IO (i.e. MIO) define the behavior. 

For details see the Zynq UltraScale+ MPSoC Register Reference

https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html

In the below example, Bank0 is the PS_MIO0..25 pins.

bank0_ctrl5 enables or disables the internal resistor, and the reset value is all 1s so the register will be enable.

The reset value of bank0_crl4 is also all 1s so the I/Os will be pulled up while the PS_POR_B is asserted.


 

 

AR# 69670
日期 05/27/2019
状态 Active
Type 综合文章
器件