AR# 69671

LogiCORE IP MIPI D-PHY v3.1 (Rev. 1) - When using 7 Series Devices to implement MIPI D-PHY TX, why do we see overshoot on the output signal during HS-->LP transmission?

描述

When implementing the MIPI D-PHY v3.1 IP (Rev. 1) (Transmitter side) for 7 Series with the OBUFTDS option enabled, why do we observe some signal overshoot during HS-->LP mode transmission?

This overshoot does not seem to affect the receiver side behavior (no error flag is triggered) but the output signal level might violate the MIPI D-PHY specification.

This issue occurs in the MIPI D-PHY (Transmitter side) for 7 Series generated from:

  • Vivado 2017.1 - MIPI D-PHY Controller v3.1
  • Vivado 2017.2 - MIPI D-PHY Controller v3.1 (Rev. 1)

解决方案

This issue occurs in the MIPI D-PHY for 7 Series, but only when generated with the OBUFTDS option enabled for the MIPI D-PHY TX configuration.

  • Vivado 2017.1 - Users should update to Vivado 2017.3 or later.
  • Vivado 2017.2 - Users can download the MIPI D-PHY patch from (Xilinx Answer 69760) to work around this issue.
  • Vivado 2017.3 - This issue is resolved in the MIPI D-PHY in Vivado 2017.3 and later.

Users should update to the latest version of the IP available.

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AR# 69671
日期 04/24/2018
状态 Active
Type 综合文章
器件 More Less
IP