Version Found: All prior to 2017.3
When you select the Clock and Data alignment as Edge (either Edge DDR or Edge DRR Clock/Strobe) the High Speed SelectIO Wizard will use SHIFT_90 for the RX_CLK_PHASE_P/_N.
When this is used the RX Delay Value should be 0.
Note: this Answer Record should not be viewed in isolation.
For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)
In Vivado 2017.2 and earlier versions, the High Speed SelectIO Wizard allowed users to select both Edge aligned and to choose an RX Delay Value.
In hardware this would result in a different Clock and Data alignment than expected.
In the 2017.3 and later versions of the High Speed SelectIO Wizard, if a non zero RX Delay Value is selected with an Edge Aligned interface, the user will be warned that BITSLICE_CONTROL uses RX_CLK_PHASE_P AND RX_CLK_PHASE_N set to SHIFT_90.
One of the used RX_BITSLICEs connected to the BITSLICE_CONTROL must set DELAY_VALUE=0 to ensure that the clock is correctly centered.