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AR# 6968

10.1 Floorplanner - "ERROR:Pack:679 - Unable to obey design constraints." (No DRC check on Virtex FF clock)


When I place two flip-flops with opposite clock polarities into the same slice in Floorplanner, then run my design through MAP, the following errors are reported on these constraints:

"ERROR:Pack:679 - Unable to obey design constraints (LOC = ...) which require the combination of the following symbols into a single slice component:

FLOP symbol ...

FLOP symbol ...

The clock signals don't agree. Please correct the design constraints accordingly."

Why does this occur?


Flip-flops with different clock polarities must be placed in separate slices. To avoid this MAP error, place flip-flops that have different clock polarity into different slices.

The Floorplanner will include more complete DRC checks in a future software release.

AR# 6968
创建日期 08/21/2007
Last Updated 12/15/2012
状态 Active
Type 综合文章