AR# 69685


Zynq UltraScale+ MPSoC, PMUFW - PS AXI interconnect performance degradation in Vivado 2017.1


When using a design in Vivado 2017.1 with PMU firmware, performance of peripherals or PL AXI interfaces is reduced relative to 2016.4.

How do I resolve this issue?


In Vivado 2017.1, PMU firmware will shutdown a PLL if no endpoint peripheral depends on that PLL, even if that PLL is used for PS interconnect switches.

For example, if the VPLL is assigned to only the TOP_SWITCH and if there is no other peripheral using the VPLL, the PMU will bypass the VPLL, causing the TOP_SWITCH to operate at PSS_REF_CLK. 

This degrades the performance of any traffic passing through the top switch interconnect.


To work around this issue in Vivado 2017.1, ensure that there are no PLLs which drive only interconnect/switch clocks, which will prevent the PLL from being idled.

This issue is fixed starting in Vivado 2017.2.


Note: When using DisplayPort, the Linux driver will attempt to change the frequency of the PLL driving the video/audio reference clock, resulting in similar symptoms to this issue.

AR# 69685
日期 10/06/2017
状态 Active
Type 综合文章
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