AR# 69760

2017.2 LogiCORE IP MIPI D-PHY v3.1 (Rev. 1) - Patch Updates for the MIPI D-PHY LogiCORE IP v3.1 (Rev. 1)

描述

This answer record contains patch updates for the MIPI D-PHY LogiCORE IP v3.1 (Rev. 1)

解决方案

This patch fixes the following issue in the LogiCORE IP MIPI D-PHY v3.1 (Rev. 1) generated from the Vivado 2017.2 design tools.

(Xilinx Answer 69671)When using 7 Series Devices to implement MIPI D-PHY TX, why do we see overshoot on the output signal during HS-->LP transmission?
(Xilinx Answer 69931)When using MIPI D-PHY TX, why is the HS-PREPARE length violating MIPI D-PHY specification version 1.1?
(Xilinx Answer 69766)When using MIPI D-PHY TX, why do we have skewed SoT signal between lanes?


See the individual Answer Record for details on which release the issue is fixed in.

Patch Installation:

Install the patch as per the instructions in the included README.txt file to resolve this issue.

附件

文件名 文件大小 File Type
AR69760_Vivado_2017_2_preliminary_rev1.zip 1 MB ZIP

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Answer Number 问答标题 问题版本 已解决问题的版本
69766 LogiCORE IP MIPI D-PHY v3.1 (Rev. 1) - When using MIPI D-PHY TX, why do we have skewed SoT signal between lanes? N/A N/A
AR# 69760
日期 04/24/2018
状态 Active
Type 综合文章
器件 More Less
Tools
IP