AR# 69766

LogiCORE IP MIPI D-PHY v3.1 (Rev. 1) - When using MIPI D-PHY TX, why do we have skewed SoT signal between lanes?


When using the MIPI D-PHY v3.1 (Rev.1) Transmitter side, there can be too much skew on the SoT signal between lanes.

This can cause errors at the MIPI receiver. This behavior varies depending on implementation results.

This issue occurs in the MIPI D-PHY (Transmitter side) generated from:

  • Vivado 2017.1 - MIPI D-PHY Controller v3.1
  • Vivado 2017.2 - MIPI D-PHY Controller v3.1 (Rev. 1)


According to the MIPI D-PHY specification version 1-1, the MIPI D-PHY transmitter output signal must have no more than +/-3.5 UI skew between lanes.

However, as a result of this issue, after implementation of the MIPI D-PHY TX, it can have skew between lanes of up to +/- 8UI.

  • Vivado 2017.1 - Users should update to Vivado 2017.4 or later.
  • Vivado 2017.2 - Users can download the MIPI D-PHY patch from (Xilinx Answer 69760) to work around this issue.
  • Vivado 2017.3 - Users should update to Vivado 2017.4 or later.
  • Vivado 2017.4 - This issue is resolved in the MIPI D-PHY in Vivado 2017.4 and later.

Users should update to the latest version of the IP.


文件名 文件大小 File Type
MIPI_spec_3.5UI.png 173 KB PNG




AR# 69766
日期 04/24/2018
状态 Active
Type 综合文章
器件 More Less