AR# 69789

UltraScale/UltraScale+ - How to change the pinouts for XAPP1274 Native Mode

描述

The XAPP1274 Asynchronous example design is for XCVU095 using Bank 67, Byte Group 2. 

Changing the pinouts requires going through the comments to adjust the design files.

解决方案

XAPP1274 design files assume RX_BITSLICE is in the lower nibble and TX_BITSLICE in the upper nibble of Byte group 2 of Bank 66 in the VCU095 device.

These settings can be customized by adjusting the generics provided in the design files. 

The following is a description for how to modify the pinouts for different devices.

Overview of Design Hierarchy

  1. Part
  2. Bank
  3. Byte Group
  4. Placing RX_BITSLICE in upper nibble and TX_BITSLICE in lower nibble
  5. Byte Group with only PLL clock source (no bitslices)
69789-1.jpg

 
This reference design uses the debug cores VIO and ILA which upon opening will typically need to be updated. 
 
For example, if the core needs to be upgraded, the following icon will appear:
 
You can also use the report_ip_status command to provide additional details on the IP status. 
 

Additional notes for XAPP1274 update:

In the initial version of XAPP1274, additional placement constraints were provided for the XCVU095.

As this is a reference design, other applications might require the logic to be moved and as such the pblock constraints that were provided for XCVU095 have been commented out to allow for better portability between different devices/banks/bytes.

Additionally, the NativePkg.vhd has been updated for the XCVU440 bank.

See (UG575) Die Level Bank Numbering Overview in Chapter 1.

 

 

1) Changing the Part

File: Byte_Top_RxTx_Prbs_IlaVio.vhd
C_Part: string := VCU095;
 

 
 

2) To change the bank:

File: Byte_Top_RxTx_Prbs_IlaVio.vhd
C_IoBank: integer :=66;
 

 

3) To change the Byte Group used:

 

File: Byte_Top_RxTx_Prbs_IlaVio.vhd
C_BytePosition: integer :=2;
 
For consistency, the ports are annotated with _0,_1,_2, _3 to denote the byte group as described in the comments. 
 
When instantiating Byte_Top_RxTx_Prbs, the generics for each byte group will be needed to allow for each byte group to be customized:
 
RxTx_Prbs_IlaVio_I_RxTx_Prbs : entity xil_defaultlib.Byte_Top_RxTx_Prbs
    generic map (
        C_Part                      => C_Part,                      --
        C_IoBank                    => C_IoBank,                --
        C_BytePosition              => C_BytePosition,          --
        C_UseTxRiu_2                => C_UseTxRiu_2,            --
        C_UseRxRiu_2                => C_UseRxRiu_2,            --
        C_TxInUpperNibble_2         => C_TxInUpperNibble_2,     --
        -- Channel 09, 08, 07
        -- Channel 07 is used as clock input for the PLLs
        C_Tx_UsedBitslices_2        => C_Tx_UsedBitslices_2,    --
        C_Rx_UsedBitslices_2        => C_Rx_UsedBitslices_2,    --
        C_FpgaClkOut_2              => C_FpgaClkOut_2,          --
        C_Tx_IoStandard_2           => C_Tx_IoStandard_2,       --
        C_Rx_IoStandard_2           => C_Rx_IoStandard_2,       --
        C_OnChipLvdsTerm_2          => C_OnChipLvdsTerm_2       --
    )
And similarly in Byte_Top_RxTx_Prbs.vhd:
 
entity Byte_Top_RxTx_Prbs is
    generic (
        C_Part                      : string := "XCVU095";
        C_IoBank                    : integer := 66;
        C_BytePosition              : integer := 2;
        C_UseTxRiu_2                : integer := 0;
        C_UseRxRiu_2                : integer := 1;
        C_TxInUpperNibble_2         : integer := 1;
        -- Channel 09, 08, 07
        -- Channel 07 is used as clock input for the PLLs
        C_Tx_UsedBitslices_2        : std_logic_vector(6 downto 0) := "0010100";
        C_Rx_UsedBitslices_2        : std_logic_vector(6 downto 0) := "0111101";
        C_FpgaClkOut_2              : integer := 1;
        C_Tx_IoStandard_2           : string := "LVDS";
        C_Rx_IoStandard_2           : string := "LVDS";
        C_OnChipLvdsTerm_2          : integer := 1;
        C_InSimulation              : string := "false"
    );
 
Byte_Top_RxTx_Prbs_I_Byte_TopNative_RxTx : entity xil_defaultlib.Byte_TopNative_RxTx
    generic map (
        C_Part                      => C_Part,                  --
        C_IoBank                    => C_IoBank,                --
        C_UseTxRiu_2                => C_UseTxRiu_2,            --
        C_UseRxRiu_2                => C_UseRxRiu_2,            --
        C_TxInUpperNibble_2         => C_TxInUpperNibble_2,     --
        -- Channel 09, 08, 07
        -- Channel 07 is used as clock input for the PLLs
        C_Tx_UsedBitslices_2        => C_Tx_UsedBitslices_2,    --
        C_Rx_UsedBitslices_2        => C_Rx_UsedBitslices_2,    --
        C_FpgaClkOut_2              => C_FpgaClkOut_2,          --
        C_Tx_IoStandard_2           => C_Tx_IoStandard_2,       --
        C_Rx_IoStandard_2           => C_Rx_IoStandard_2,       --
        C_OnChipLvdsTerm_2          => C_OnChipLvdsTerm_2,      --
        C_InSimulation              => C_InSimulation           --
    )
In Byte_TopNative_RxTx.vhd, comment or uncomment the byte groups that are used:
 
entity Byte_TopNative_RxTx is
    generic (
        C_Part                      : string := "XCKU060";
        C_IoBank                    : integer := 68;
        C_InSimulation              : string := "false";
        ---- Byte_3: Channel 12, 11, 10
        --C_UseTxRiu_3                : integer := 0;
        --C_UseRxRiu_3                : integer := 1;
        --C_TxInUpperNibble_3         : integer := 1;
        --C_Tx_UsedBitslices_3        : std_logic_vector(6 downto 0) := "0010101";
        --C_Rx_UsedBitslices_3        : std_logic_vector(6 downto 0) := "0111111";
        --C_FpgaClkOut_3              : integer := 0;
        --C_Tx_IoStandard_3           : string := "LVDS";
        --C_Rx_IoStandard_3           : string := "LVDS";
        --C_OnChipLvdsTerm_3          : integer := 1;
        -- Byte_2: Channel 09, 08, 07
        -- Byte_2: Channel 07 is used as clock input for the PLLs
        C_UseTxRiu_2                : integer := 0;
        C_UseRxRiu_2                : integer := 1;
        C_TxInUpperNibble_2         : integer := 1;
        C_Tx_UsedBitslices_2        : std_logic_vector(6 downto 0) := "0010100";
        C_Rx_UsedBitslices_2        : std_logic_vector(6 downto 0) := "0111101";
        C_FpgaClkOut_2              : integer := 1;
        C_Tx_IoStandard_2           : string := "LVDS";
        C_Rx_IoStandard_2           : string := "LVDS";
        C_OnChipLvdsTerm_2          : integer := 1
        ---- Byte_1: Channel 06, 05, 04
        --C_UseTxRiu_1                : integer := 0;
        --C_UseRxRiu_1                : integer := 1;
        --C_TxInUpperNibble_1         : integer := 1;
        --C_Tx_UsedBitslices_1        : std_logic_vector(6 downto 0) := "0010101";
        --C_Rx_UsedBitslices_1        : std_logic_vector(6 downto 0) := "0111111";
        --C_FpgaClkOut_1              : integer := 0;
        --C_Tx_IoStandard_1           : string := "LVDS";
        --C_Rx_IoStandard_1           : string := "LVDS";
        --C_OnChipLvdsTerm_1          : integer := 1;
        ---- Byte_0: Channel 03, 02, 01
        --C_UseTxRiu_0                : integer := 0;
        --C_UseRxRiu_0                : integer := 1;
        --C_TxInUpperNibble_0         : integer := 1;
        --C_Tx_UsedBitslices_0        : std_logic_vector(6 downto 0) := "0010101";
        --C_Rx_UsedBitslices_0        : std_logic_vector(6 downto 0) := "0111111";
        --C_FpgaClkOut_0              : integer := 0;
        --C_Tx_IoStandard_0           : string := "LVDS";
        --C_Rx_IoStandard_0           : string := "LVDS";
        --C_OnChipLvdsTerm_0          : integer := 1
    );
 
 

For every byte group, the following settings will determine which pins are available and how the bitslices will be used:

        C_UseTxRiu_2                : integer := 0;
        C_UseRxRiu_2                : integer := 1;
        C_TxInUpperNibble_2         : integer := 1;
        -- Channel 09, 08, 07
        -- Channel 07 is used as clock input for the PLLs
        C_Tx_UsedBitslices_2        : std_logic_vector(6 downto 0) := "0010100";
        C_Rx_UsedBitslices_2        : std_logic_vector(6 downto 0) := "0111101";
        C_FpgaClkOut_2              : integer := 1;
        C_Tx_IoStandard_2           : string := "LVDS";
        C_Rx_IoStandard_2           : string := "LVDS";
        C_OnChipLvdsTerm_2          : integer := 1;
        C_InSimulation              : string := "false"

 

Typically the RIU interface will be needed for the RX interface to be able to control the RX_BITSLICE for alignment:
 
        C_UseTxRiu_2                : integer := 0;
        C_UseRxRiu_2                : integer := 1;
 
For each nibble, C_Rx_UsedBitslices_# will determine which bitslices are used.  
 
For example, given C_Rx_UsedBitslices_2        : std_logic_vector(6 downto 0) := "0111101";
 
   0111101            
   ||||| |\_0P BITSLICE0 enabled
   ||||| \__0N BITSLICE1 disabled
   ||||\  ___1P BITSLICE2 enabled
   |||\_ ___1N BITSLICE3 enabled
   ||\__ ___2P BITSLICE4 enabled
   |\______2N BITSLICE5 enabled
   \_______3  BITSLICE6 disabled Upper Nibble only
 
Similarly C_Tx_UsedBitslices_# will determines the TX_BITSLICEs that will be used. 
 
For differential outputs, only the bitslice within the master differential pair can be enabled:
 
   0010101            
   ||||| |\_0P BITSLICE0 enabled
   ||||| \__0N BITSLICE1 disabled
   ||||\  ___1P BITSLICE2 enabled
   |||\_ ___1N BITSLICE3 disabled
   ||\__ ___2P BITSLICE4 enabled
   |\______2N BITSLICE5 disabled
   \_______3  BITSLICE6 disabled Upper Nibble only
 

 

4) Placing RX_BITSLICE in upper nibble and TX_BITSLICE in lower nibble

TX_BITSLICEs can be placed in either the upper nibble or lower nibble based on C_TXInUpperNibble_#. 
 
To allow the native design to allow the TX_BITSLICE logic to be placed in either the upper or lower nibble, the C_TxInUpperNibble_# generic must be used to allow the ports to adjust for upper/lower nibble.
 

Byte_TopNative_RxTx.vhd:

signal IntBase_Idly_Ce_2           : std_logic_vector((7-C_TxInUpperNibble_2)-1 downto 0); --(5 downto 0);
signal IntBase_Idly_Inc_2          : std_logic_vector((7-C_TxInUpperNibble_2)-1 downto 0); --(5 downto 0);
signal IntBase_Idly_Load_2         : std_logic_vector((7-C_TxInUpperNibble_2)-1 downto 0); --(5 downto 0);
signal IntBase_Idly_CntValueIn_2   : std_logic_vector( ((7-C_TxInUpperNibble_2)*9)-1 downto 0); --(53 downto 0);
signal IntBase_Idly_CntValueOut_2  : std_logic_vector( ((7-C_TxInUpperNibble_2)*9)-1 downto 0); --(53 downto 0);
signal IntBase_Rx_BtVal_2          : std_logic_vector(8 downto 0);
signal IntBase_Rx_Fifo_Rd_En_2     : std_logic_vector( (7 - C_TxInUpperNibble_2 - 1) downto  0 );  --(5 downto 0);--in [(7-C_TxInUpperNibble_3)-1:0]
signal IntBase_Rx_Fifo_Empty_2     : std_logic_vector( (7 - C_TxInUpperNibble_2 - 1) downto  0 );  --(5 downto 0);
signal IntBase_Tx_T_In_2           : std_logic_vector(( 6 + C_TxInUpperNibble_2) - 1 downto 0);  --(6 downto 0);
signal IntBase_Tx_D_In_2           : std_logic_vector(((6 + C_TxInUpperNibble_2) * 8) - 1 downto 0); --(55 downto 0);
signal IntBase_Rx_Q_Out_2          : std_logic_vector(((7-C_TxInUpperNibble_2)*4)-1 downto 0); --(23 downto 0);
 
IntBase_Tx_T_In_2                  <= LowVec(( 6 + C_TxInUpperNibble_2) - 1 downto 0);  --(6 downto 0);
 
Base_Idly_Ce_2             => LowVec( (7 - C_TxInUpperNibble_2 - 1) downto  0 ),  --(5 downto 0), -- in [(7-C_TxInUpperNibble_2)-1:0]
Base_Idly_Inc_2            => LowVec( (7 - C_TxInUpperNibble_2 - 1) downto  0 ),  --(5 downto 0), -- in [(7-C_TxInUpperNibble_2)-1:0]
 
IntBase_Tx_D_In_2(((7-C_TxInUpperNibble_2)*4)-1 downto 40)    <= LowVec(( (1+C_TxInUpperNibble_2 )* 8 -1) downto 0); --IntBase_Tx_D_In_2(55 downto 40)    <= LowVec(15 downto 0);
 
IntBase_Tx_D_In_2(((7-C_TxInUpperNibble_2)*4)-1 downto 40)    <= LowVec(( (1+C_TxInUpperNibble_2 )* 8 -1) downto 0); --IntBase_Tx_D_In_2(55 downto 40)    <= LowVec(15 downto 0);
 

Bank.vhd:

        -- Control the BITSLICEs
        Base_Rx_Fifo_Rd_En_2       : in std_logic_vector((7-C_TxInUpperNibble_2)-1 downto 0); --
        Base_Rx_Fifo_Empty_2       : out std_logic_vector((7-C_TxInUpperNibble_2)-1 downto 0); --
 
        -- Delay lines
        Base_Idly_Ce_2             : in std_logic_vector((7-C_TxInUpperNibble_2)-1 downto 0); --
        Base_Idly_Inc_2            : in std_logic_vector((7-C_TxInUpperNibble_2)-1 downto 0); --
        Base_Idly_Load_2           : in std_logic_vector((7-C_TxInUpperNibble_2)-1 downto 0); --
        Base_Idly_CntValueIn_2     : in std_logic_vector(((7-C_TxInUpperNibble_2)*9)-1 downto 0); --
        Base_Idly_CntValueOut_2    : out std_logic_vector(((7-C_TxInUpperNibble_2)*9)-1 downto 0); --
 
        -- FPGA fabric connections
        Base_Tx_T_In_2             : in std_logic_vector((6+C_TxInUpperNibble_2)-1 downto 0); --
        Base_Tx_D_In_2             : in std_logic_vector(((6+C_TxInUpperNibble_2)*8)-1 downto 0); --
        Base_Rx_Q_Out_2            : out std_logic_vector(((7-C_TxInUpperNibble_2)*4)-1 downto 0); --
.
        Base_Odly_Ce               => LowVec(  (6 + C_TxInUpperNibble_2 - 1) downto 0), --jimt_lower LowVec(6 downto 0), -- [(6+C_TxInUpperNibble)-1:0]
        Base_Odly_Inc              => LowVec(  (6 + C_TxInUpperNibble_2 - 1) downto 0), --jimt_lower LowVec(6 downto 0), -- [(6+C_TxInUpperNibble)-1:0]
        Base_Odly_Load             => LowVec(  (6 + C_TxInUpperNibble_2 - 1) downto 0), --jimt_lower LowVec(6 downto 0), -- [(6+C_TxInUpperNibble)-1:0]
        Base_Odly_CntValueIn       => LowVec( ((6 + C_TxInUpperNibble_2) * 9 - 1) downto 0), --jimt_lower LowVec(62 downto 0), -- [((6+C_TxInUpperNibble)*9)-1:0]
 

 


5) Routing only the clock to Byte Group 2:

 
The differential clock is routed to Byte group 2, BITSLICE0 which can be a strobe/clock and also used for routing to the PLL.
 
In the event that only the clock was being used, the following is a guideline for how to set up the generics to route the clock to the PLL:
 
        C_UseTxRiu_2                : integer := 0;
        C_UseRxRiu_2                : integer := 0;
        C_TxInUpperNibble_2         : integer := 1;
             -- Channel 9, 8, 7
        C_Tx_UsedBitslices_2        : std_logic_vector(6 downto 0) := "0000000";
        C_Rx_UsedBitslices_2        : std_logic_vector(6 downto 0) := "0000000";--jimt changed from original clocking scheme "0111100";
        C_FpgaClkOut_2              : integer := 1; --<--- Use channel 6 as clock input
        C_Tx_IoStandard_2           : string := "LVDS";
        C_Rx_IoStandard_2           : string := "LVDS";
        C_OnChipLvdsTerm_2          : integer := 1;
AR# 69789
日期 10/17/2017
状态 Active
Type 综合文章
器件 More Less