This answer record contains the Release Notes and Known Issues for the Zynq UltraScale+ RF Data Converter LogiCORE IP and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2018.1 and newer tools.
Supported devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
Alternatively, see the Change Log Answer Record: (Xilinx Answer 69701)
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Core Version||Vivado Tools Version|
Known and Resolved Issues
The following table provides known issues for the Zynq UltraScale+ RF Data Converter LogiCORE IP.
|Answer Record||Title||Version Found||Version Resolved|
|(Xilinx Answer 71077)||Zynq UltraScale+ RFSoC: Tactical Patch to fix issues with Generating IP example design on Windows||v2.0||v2.0.1|
|(Xilinx Answer 70889)||Zynq UltraScale+ RFSoC: IP will not generate when internal PLL is used and DAC Sample rate is >6.4GSPS||v2.0||v2.0.1|
04/04/2018 - Initial Release