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AR# 69907

LogiCORE IP Zynq UltraScale+ RF Data Converter - Release Notes and Known Issues for Vivado 2018.1 and newer tools

描述

This answer record contains the Release Notes and Known Issues for the Zynq UltraScale+ RF Data Converter LogiCORE IP and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2018.1 and newer tools.

解决方案

General Information

Supported devices can be found in the following three locations:

  • Zynq UltraScale+ RF Data Converter LogiCORE IP Product Guide
  • Zynq UltraScale+ RF Data Converter LogiCORE IP Product Page
  • Open the Vivado tool -> IP Catalog, right-click on an IP and select Compatible Families.

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Alternatively, see the Change Log Answer Record: (Xilinx Answer 69701)

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version
2.0.12018.2
2.02018.1
1.12017.4
1.12017.3
1.02017.2
1.02017.1


Known and Resolved Issues

The following table provides known issues for the Zynq UltraScale+ RF Data Converter LogiCORE IP.

Answer RecordTitle Version FoundVersion Resolved
(Xilinx Answer 71077)Zynq UltraScale+ RFSoC: Tactical Patch to fix issues with Generating IP example design on Windowsv2.0v2.0.1
(Xilinx Answer 70889)Zynq UltraScale+ RFSoC: IP will not generate when internal PLL is used and DAC Sample rate is >6.4GSPSv2.0v2.0.1


Revision History

04/04/2018 - Initial Release

AR# 69907
日期 05/16/2018
状态 Active
Type 综合文章
器件
Tools
的页面