AR# 69927

|

Zynq UltraScale+ MPSoC Controller for PCI Express (Vivado 2017.2) - Data Link Layer Link Active status bit in Link Status Register

描述

When the Root Port PS-PCIe core link is up, it is able to access the downstream endpoints.

However, the Data Link Layer Link Active status bit in Link Status Register still shows '0'.

解决方案

In order for the Data Link Layer Active status bit in the Link Status Register to be set correctly, the "attr_link_cap_dll_link_active_reporting_cap" bit of the ATTR_35 (PCOE_ATTRIB) register at address 0xFD48008C should be set. 

More information on this register can be found in (UG1087).

Revision History:

10/05/2017 - Initial Release

AR# 69927
日期 10/06/2017
状态 Active
Type 综合文章
IP
People Also Viewed