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AR# 69947

UltraScale Memory IP designs giving hold violations

描述

Version Found: DDR4 v2.2 (Rev. 1), DDR3 v1.4 (Rev. 1), RLDRAM3 v1.4 (Rev. 1), QDRII+ v1.4 (Rev. 1), QDRIV v2.0 (Rev. 1), LPDDR3 v1.0 (Rev. 1)

Version Resolved: See (Xilinx Answer 58435)

3 out of 600 builds give hold violations.

解决方案

If you encounter this issue, you can try to reimplement, change implementation strategy, or use a Pblock around the memory IP.

If you are unable to close timing please open a Service Request with Xilinx support.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
58435 UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues N/A N/A
AR# 69947
日期 12/20/2017
状态 Active
Type 已知问题
器件
IP More Less
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