AR# 69960


Zynq UltraScale+ MPSoC, Zynq-7000, Vivado 2017.3 - Upgrading to 2017.3 without validating can corrupt the Processing System Block


If a design with a Zynq-7000 or Zynq UltraScale+ block is modified but not validated before upgrading in Vivado 2017.3, the IP block can become corrupted, resulting in incorrect operation.


To work around this issue, be sure to validate the design before opening/upgrading the design in Vivado 2017.3.

If the design is upgraded to Vivado 2017.3 without validation, the PS block can instead be replaced - this can be accomplished by parameterizing a new PS block and then using the replace_bd_cell old_instname new_instname Tcl command to swap the IP instances without having to reconnect interfaces.

For designs unable to be validated, a patch is attached, which can be used in Vivado 2017.3 and Vivado 2017.3.1.

This issue will be fixed starting in Vivado 2017.4.


文件名 文件大小 File Type 21 MB ZIP



AR# 69960
日期 10/25/2017
状态 Active
Type 综合文章
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