AR# 70041

LogiCORE IP SMPTE SD/HD/3G-SDI (SMPTE SDI) v3.0 - IP Latency Information SMPTE SDI IP in 3G-SDI mode


(PG071) does not mention IP latency information for SMPTE SD/HD/3G-SDI TX/RX IP in 3G-SDI mode.


IP Latency Information for SMPTE SD/HD/3G-SDI IP in 3G-SDI mode is described in this Answer Record.

The native SDI TX input stream to SDI TX IP output == 17 clock cycles of tx_usrclk
The RX SDI IP input to Native RX SDI data stream output == 21 clock cycles of rx_usrclk

Please note that this latency information:

  1. Does not include transceiver part latency
  2. Assumes that the SDI IP is already locked


This Answer Record will be removed after this latency information is updated in (PG071).




Answer Number 问答标题 问题版本 已解决问题的版本
54531 LogiCORE IP SMPTE SD/HD/3G-SDI (SMPTE SDI) - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 70041
日期 01/15/2018
状态 Active
Type 综合文章