AR# 70133


Zynq UltraScale+ MPSoC: Secure Boot fails without FSBL prints on the UART


I am booting securely on Zynq UltraScale+ MPSoC but do not see any FSBL prints on the UART console.

By reading the JTAG_ERROR_STATUS using Vivado, I confirm that the CSU ROM successfully completed the FSBL loading and handoff.

As there are no prints on the UART console, the FSBL (most likely) is hanging during the execution of the psu_int() function.


When booting securely, all of the debug component in the device are kept under reset and the register CRL_APB.RST_LPD_DBG is kept at 0x33. See (UG1087) for details on the register.

An access to any of these debug modules (for example TPIU or coresight_uart (UART over JTAG)) would cause the system to hang.

You need to make sure that psu_init() is NOT accessing any debug module.

A quick test to diagnose that this is the issue is to add Xil_Out32(0xFF5E0240,0x0); right before the call to psu_init().

If that write fixes the boot issue, then psu_init() is accessing a debug module.

Examples of configurations to avoid are:

  • TRACE port enabled in Vivado which translates to TPIU configuration writes.
  • UART over JTAG selected in the FSBL BSP which translates to coresight configuration writes.
AR# 70133
日期 11/15/2017
状态 Active
Type 综合文章
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